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  • Interconnect Watch: 3 Chip Design Merits for Network Applications

    The countdown to the end of Moore's Law is coinciding with the rising complexity in system-on-chip (SoC) designs. And that's not a mere coincidence. The leverage that has long been coming from shrinking process nodes in terms of cost, performance and power benefits is now increasingly being accomplished through greater efficiency in SoC designs.

    Take, for instance, interconnect, one of the few configurable venues left on the SoC real-estate. So far, internal chip design teams have been relying on legacy interconnect technologies such as hierarchical bus and configurable crossbar. However, cost imperatives, time-to-market pressure, and design challenges like routing congestion and place-and-route issues are forcing SoC designers to consider the interconnect IP implementations.

    Montage Technology, a chip supplier for home entertainment and cloud computing markets, has licensed Arteris FlexNoC IP for its digital set-top box (STB) chipsets. Arteris' network-on-chip (NoC) technology alleviates bottlenecks in moving large blocks of data by packetizing data and serializing transmission over fewer wires than required in other interconnect technologies.

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    Interconnect architecture for an STB chipset

    The market for STB-like devices is essentially flat, but the technology content inside them is increasing. For markets like China, the over-the-top (OTT) STB and other media server devices have the opportunity to become the hub, where a number of home entertainment and consumer electronics devices can be connected.

    Next, two of the world's largest enterprise SSD manufacturers have licensed Arteris FlexNoC interconnect IP for use as the communications backbone in their SSD controller chipsets. So what makes interconnect IP solutions like Arteris FlexNoC appealing for network-centric chipset designs?

    The blog takes a peek at three design venues that particularly suit SoCs for moving large blocks of data very quickly.

    Bandwidth and Latency Management

    The bandwidth and latency features are intrinsically linked to network communications, and both of these features come under the requirement commonly known as Quality-of-Service or QoS. The latency- and bandwidth-related QoS requirements often conflict in a complex system, and to address these conflicts, Arteris' on-chip interconnect technology implements cascaded arbitration throughout the NoC framework.

    Arbiters at each switch make a cascade that is needed for timing closure. That allows simpler and lightweight logic, which in turn, leads to less area, lower cost and power savings. Master starvation and head-of-line (HOL) blocking performance limitations common in data networks are addressed by communication between arbiters that allow for Pressure and Hurry.

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    Communication between arbiters for managing heterogeneous traffic

    Pressure pushes a pending transaction that is blocking a higher priority transaction. Hurry forces a response to return as soon as possible. The end-to-end QoS—from initiator/master to target/slave—and data traffic arbitration features offered by the Arteris FlexNoC interconnect fabric can play an important role in facilitating high-bandwidth video streams and low-latency on-chip communications.

    Memory Efficiency

    For home entertainment products like OTT STB, contention for memory is of extreme importance because of the mix of one or more decoded video streams as well as audio and overlays. That makes efficient DRAM utilization a key requirement in optimal system-wide performance.

    Arteris FlexNoC's FlexMem memory scheduler ensures that transactions are ordered properly to meet the QoS requirements dictated by the user. Moreover, it ensures that the memory controller does not unnecessarily reorder these transactions.

    The memory scheduler logic understands the QoS scheme and sends data to the protocol controller to ensure that system-wide QoS is met; not just memory utilization and efficiency goals in isolation.

    The Arteris FlexNoC memory scheduler also implements reorder buffering to accommodate LPDDR4 per-bank refresh. All-bank refresh means the whole die is locked out during refresh, while in per-bank refresh, one bank is locked out at a time during refresh but other seven banks are available. Here, memory scheduler indicates when to refresh and which banks.

    On-chip Data Security

    Security is a growing concern in the next-generation networking environments like the Internet of Things (IoT). Case in point: SSD controller SoCs must protect data contents not only within processing units and memories but also in on-chip communications between them.

    Arteris FlexNoC interconnect IP features ECC and parity data protection that make it easy to set up, test and check the composition of on-chip data flows in real-time. Moreover, FlexNoC fabric natively supports the ARM Cortex-R5 and Cortex-R7 processor ECC and parity data protection schemes.

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    FlexNoC Resilience Package is developed for safety-related SoC designs in the automotive, industrial and medical markets

    Next, Arteris makes available data security features such as redundancy, duplication and built-in system test (BIST) with the optional FlexNoC Resilience Package.

    Also read:

    SSD Storage Chips: Basic Interconnect Considerations

    Is Interconnect Ready for Post-mobile SoCs?

    Rockchip Bets on Arteris FlexNoC Interconnect IP to Leapfrog SoC Design