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  • Krivi Specialty I/O Library Support UMC 28nm

    There is an industry consensus about 28nm, the technology node is here to stay, and to stay for very long. If we except 20nm node, which by opposition will have a very short lifetime, 28nm is the last node following the economic part of Moore’s law: designing on smaller technology allows building cheaper IC when you integrate the same functions, or to integrate two fold more gates at the same price. If a chip maker has deep enough pocket to afford huge development cost (R&D cost in the $80 to $100 million) he can target 16FF or even 10FF, the resulting IC will be faster and lower power but not necessarily cheaper than on 28nm, as we can see on below picture.

    Article: Two New Board Members at Mentor Graphics-chips.jpg

    For a vast majority of the semiconductor industry targeting 28nm and above nodes it’s a very good news to know that the 28nm offer will be as large as possible, including UMC on top of TSMC and GlobalFoundries (Samsung focusing on a few customers asking for very large production volume). In this context, it’s important for potential UMC customer to rely on an offer as complete as possible, including specialty I/O pads. Krivi has announced the validation of IO pad library platform at UMC 28nm technology.

    This IO platform supports wide variety of interface standards such as DDR, LVDS, and Memory card super combo IO libraries. We often write about SuperSpeed USB, PCI Express 3.0 or HDMI 2.0, these SerDes based protocol standards, essential to design SoC for consumer, networking or PC peripheral application. But to design a SoC you will also need to integrate these specialties I/Os and you expect these IO libraries to be proven in test silicon for their compliance to respective electrical standards, ESD and latch-up performance. Your boss may accept that the first release of the 16G PCIe 4.0 PHY fail to be 100% at spec… but certainly not if you SoC prototype don’t work due to a failing LVDS I/O.

    Article: Two New Board Members at Mentor Graphics-krivi-co-founders.jpg

    According with Sivaramakrishnan Subramanian, Co-founder and Senior Principal engineer at Krivi: “Our specialty IO platform gives great flexibility to SoC and IP companies using UMC 28nm technologies to pick off-the-shelf IO pads that match or exceed best power, performance and area in industry”. If you don’t know Krivi Semiconductor, you most probably know ARM Ltd. The team in charge of the DDR3 PHY design within ARM has spin off to create Krivi in 2013. The same team has designed a specialty I/O platform supporting:

    • Universal DDR IO pad library supports all popular DDR standards like DDR4, DDR3/3U/3L, LPDDR3, LPDDR2, HSTL class-I and RLDRAM-3 etc. This library works at a maximum speed of 2.667Gbps in HLP process technology and boasts of having industry's smallest foot-print. This library is designed with an aggressive power target of receiving data at 1mW/Gbps.
    • LVDS and Sub-LVDS combo IO library have data input and output cells along with an in-built Bandgap voltage reference cell for biasing. This IO pad meets TIA/EIA-644-A and SMIA 1.0 Part 2: CCP2 Sub-LVDS standards while working at top speed of 2Gbps and 1.6Gbps respectively.
    • Memory card I/O pad supports interface signaling ranging from 1.2V to 3.3V while using 1.8V gate oxide IO devices. This bi-directional I/O pad supports eMMC and UHS-I SD card standards.
    • SLVS, SubLVDS and SD UHS-II combo IO pad library is designed to meet JESD8-13, SMIA 1.0 Part 2: CCP2, and UHS-II SD card association standards with a top speed of 1.56Gbps.


    Large semi or IP companies have moved IP design resources to India in early 2000’s and we can clearly identify start-up issued from these chip or IP makers, especially in the mixed-signal area, like Cosmic Circuits (acquired by Cadence in 2012), Silabtech (spin-off of OMAP PHY design team from TI) or Krivi, in charge of DDRn PHY IP with ARM. These design teams have the same level of experience and excellence than their counterpart working with the well-known IP vendors, and UMC choice make sense, according with Shih-Chin Lin:

    “UMC has built a strong library, IP and design support environment for customers designing into our high volume production 28nm technology,” said Shih-Chin Lin, senior director of UMC’s IP & Design Support division at UMC. “With the addition of the IO Alcor platform from Krivi, our mutual customers now have access to a valuable resource that will allow them to seamlessly integrate a wide variety of high speed memory IO into their SoC design.”