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  • FD-SOI: a Gentle Introduction

    Over the last couple of weeks, FD-SOI has been in the news with GlobalFoundries announcement of a 22nm FD-SOI process that will run in the Dresden Fab. Also, earlier in the week I talked to Thomas Skotnicki about the saga (and it is a saga) of how FD-SOI got from his PhD thesis to volume manufacturing and global deployment. But there is a lot less knowledge around about FD-SOI than there is about FinFET so I thought it would be good to go back and see where the motivation for a process like that came from.

    See GlobalFoundries 22nm FD-SOI: What Happens When

    See Thomas Skotnicki: FD-SOI 26 Years in the Making

    imec's annual report 2011-fdsoi1.jpg

    By 28/20nm planar processes were running into problems. The channel area underneath the gate was getting very short and the gate was no longer powerful enough to control it properly. It could control the top part of the channel but the further from the gate the less the control. In particular, when the gate was off there were paths between source and drain that remained on and so there was very high leakage. See the diagram above. It was clear that a new transistor architecture would be required.

    The basic constraint was that all of the channel needed to be close to the gate so that it could be controlled properly. One way to do this was to make the channel into a thin vertical fin (like a shark's fin, that is where the name comes from) and wrap the gate around it which gives you FinFET. Since the fin is thin, it is never far from the gate and control is good and leakage is low.
    imec's annual report 2011-fdsoi2.jpg

    The alternative is to go horizontal. If a thin channel is put on top of an insulator, and the gate is built on top of that then there is once again good control and low leakage. There are simply no paths through the channel that are far from the gate and so poorly controlled because the insulator is...well, an insulator. Current cannot flow there. The transistor is not quite as good as FinFET since it only controls one side of the channel, but it is a lot easier to manufacture. That is thick-box FD-SOI (box just stands for buried oxide, the insulator underneath the channel). If, however, the box is very thin then in effect the substrate itself becomes a sort of second back gate and can further be used to control the channel, not to turn it on and off but to affect its performance. See the diagram above.
    imec's annual report 2011-fdsoi3.jpg

    The above diagram shows how forward body bias (FBB) works. FBB of up to about 1.5V can be applied (GF reckon they can go to 1.8V at 22nm). When higher performance is required the FBB is applied. The transistors are faster at a cost of slightly higher leakage. When the design is in a standby mode of some sort then the FBB can be removed to reduce the leakage again. Alternatively, the power supply voltage can be reduced, which would slow the transistor down too much to meet timing, and then FBB can be used to speed it up again. But the voltage is still down, reducing leakage and, of course, dramatically reducing dynamic power (voltage is squared in the power equation).
    imec's annual report 2011-gf3.jpg
    Since the FBB is under software control, it can be used very much like dynamic voltage and frequency scaling (DVFS) under software control and the EDA and signoff flows required for FBB are almost identical. The above diagram shows for the GF 22FDX process the effect. The red line is 28HKMG, the green is 22FDX and the blue is 22FDX with FBB of 1.5V.
    imec's annual report 2011-fdsoi4.jpg

    FBB can also be used to reduce overdesign by recentering the parts and move slow and typical parts to the fast end of the distribution, and to narrow the distribution. One of the big selling points of the GlobalFoundries 22FDX process(es) is that it can reduce the power supply voltage all the way to 0.4V.
    imec's annual report 2011-fdsoi4.jpg

    You might have heard that FD-SOI uses an expensive starting material (wafer blank) and that is true. But, in effect, that is because a couple of "mask steps" have already been done. I put it in quotes since no masks are involved. The wafer blank looks like the above picture. For 28nm the top silicon layer is 12nm thick and the box is 20nm. Some (5-6nm) of the top silicon is lost during processing leaving a channel depth of about 6nm. For 22nm these numbers are further reduced. The rest of the process is actually simpler than the equivalent bulk process involving fewer masks and fewer mask steps (and about half the number of FEOL masks as the equivalent FinFET process, although the BEOL is, of course, the same).

    Any SOI technology has some inherent advantages over bulk:
    • no well taps required
    • isolation makes on-chip RF much simpler
    • higher resistance to latch up
    • inherently more radiation hard (in fact SOI was first used in space)
    • reduced parasitic capacitance (this is one of the challenges with FinFET)

    Thin box FD-SOI has the further advantage of forward body bias. And the FD (fully depeleted) part makes manufacture easier since zero is a very easy number to keep under control.