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  • Benefits of RTL Power Budgeting

    Only one company at the recent DAC conference and exhibit had a set of four interacting disciplines: Fluids, Structures, Electronics and Systems. Did you guess that the company was ANSYS? I get so IC focused at times that I almost forget that chips plug into boards, that boards become systems, and that systems drive and control mechanical devices where fluid airflow is a design challenge. One presentation made by ANSYS at #52DAC was titled, "Driving Low-power Design with Physical-aware RTL Power Budgeting Methodology", and it caught my attention because of the EDA focus. ANSYS acquired Apache back in 2011, so during the past four years their electronics software has continued to meet familiar challenges like:

    • Power Budgeting
    • SoC Analysis
    • IP Validation
    • ESD Protection
    • IC/System Co-design
    • IO DDR Design
    • Thermal Planning
    • Package/PCB Electrical
    • Mechanical Stress



    Who will Apple partner with at 20nm: TSMC, Intel, Both, or Neither?-ansys-technologies.jpg

    Related - Trends in Automotive Electronics at #52DAC

    The big idea behind managing power during the design phase is to focus on tools for RTL designers, where they can change their code even before logic synthesis and physical implementation in order to achieve the greatest power reduction. With this mindset you then want a design for power environment where it's possible to:

    • Trade-off power, performance and area
    • Perform voltage and power domain planning
    • Use block-level clock and data gating techniques
    • Eliminate redundant activity


    With the ANSYS approach there are six steps that lead to a design that is optimized for low-power:

    Who will Apple partner with at 20nm: TSMC, Intel, Both, or Neither?-best-practices-low-power-rtl-design.jpg

    Related - A Key Partner in the Semiconductor Ecosystem

    Perform Design Trade-offs at RTL
    It's easiest at the RTL level to look at implementing hardware in various approaches like creating an IFFT as pipelined, combinational or folded architecture. While at RTL you can quickly estimate power dissipation for each approach and choose the one that meets your power, performance and area goals.

    Profile Design Activity
    Using a tool like PowerArtist an RTL designer can actually profile design activity to identify power-critical windows, qualify vectors per mode, and identify any wasted activity.

    Who will Apple partner with at 20nm: TSMC, Intel, Both, or Neither?-profile-design-activity.jpg

    Check Power versus Budget, Early
    During RTL coding you should be looking at power in all of its forms: Average, Peak, Waveforms. This kind of early feedback enables an engineer to decide on a package type, decoupling capacitors, and grid design. Understanding the early power numbers across the hierarchy, by category (function, static or dynamic), by power mode will help identify all contributions to total power dissipation.

    Related - Getting the Best Dynamic Power Analysis Numbers

    Early RTL power numbers can be within 15% of implementation values by using PowerArtist in conjunction with PACE models. In one case study NVIDIA compared RTL power numbers versus gate-level and saw results within 15%, while the RTL power numbers were calculated about 30X faster than gate-level values.

    Identify and Debug Power Hotspots
    There are a couple of approaches to debugging power hotspots: Graphic or Tcl-based. With the graphical approach you can spot anomalies in power by browsing for absolute power values, relative power values, cross-probing RTL to schematics, or using power metrics.

    Who will Apple partner with at 20nm: TSMC, Intel, Both, or Neither?-visually-debug-power-anomalies.jpg

    With the Tcl language a designer can get quick access to both power and design properties. Power metrics can be listed on each block of your design hierarchy, or by clock domains, or even down to the flop and latch levels.

    Reduce Power Early at RTL
    Two power reduction techniques that restructure your RTL are block-level clock gating and block-level data gating. There are even some built-in automation with PowerArtist that identify logic for clock gating, memory subsytem optimization, and reports on eliminating redundant activity.

    Track Power via Regressions
    Software development teams have used the concept of regression testing to improve code quality, and the same approach also improves the power reduction methodology so that your team can visually monitor power usage throughout the entire development cycle. You can run daily block-level power regressions, weekly chip-level power regressions, in order track your power change and track reduction opportunities.

    Related - Will your next SoC fail because of power noise integrity in IP blocks?

    Summary
    The proof in any EDA methodology for electronics design is customer adoption, and at the DAC show there were plenty of ANSYS customers at hand, such as: Avago, Cavium, ClariPhy, Emulex, Freescale, Infineon, Intel, Mediatek, Microsoft, Qualcomm, Samsung and Tesla.