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  • Leveraging Power Reduction Techniques for MCU Based SoCs

    Dolphin Integration launched a new 32-bit microcontroller, RISC-351 Zephyr, targeting low-power SoCs for IoT-like competitive markets taking into consideration three angles for optimization of power consumption: architectural, memory and software.

    Architecture Angle
    As a reminder, 8-bit versus 16-bit versus 32-bit applies to 3 dimensions independently: instruction code, addressing space, and word width. The Arithmetic Logic Unit (ALU) performs operations on the word width. Thanks to an innovative instruction set and core micro-architecture, the RISC-351 Zephyr offers the unique flexibility of dealing with 8, 16, and 32-bit words using dedicated instructions and minimum sufficient data path in order to achieve low power consumption and small silicon area at subsystem-level (including program and data memories).

    Beyond clock gating, which has been carefully implemented so that most functional blocks can be separately gated, RISC-351 Zephyr is available in a Retention Ready (RR) version which supports efficient power gating in 'Deep Sleep' mode. The advantage of this mode is that only the registers, which hold the needed information to wake-up in the same state, are kept in retention. All other logic is completely switched off.

    Memory Angle
    Memories play a major part in the overall power consumption of any microcontroller based subsystem. The Reduced Instruction Set of Zephyr achieves unsurpassed code density thanks to a smart use of variable instruction sizes whenever possible. This either enables adding more functionalities in the program or selecting smaller program memories, whether RAMs or NVMs (and thus saving leakage power).

    The RISC-351 Zephyr also features an innovative pre-fetch interface dedicated to minimizing the number of accesses to the program memory by eliminating unnecessary ones. The number of accesses is reduced by 15% compared to conventional 32-bit low-power MCUs.

    In addition, Dolphin Integration proposes an instruction cache-controller (R-Stratus-LP) which has been specifically designed to reduce power consumption and access time of embedded Flash and EEPROM memories by more than three times. The R-Stratus-LP offers highest hit rates because of its on-the-fly parameterized associativity ways and line size change capabilities.

    Article: Such a small piece of Silicon, so strategic PHY IP-zephyr.jpg


    Software Angle
    A complete and innovative Integrated Development Environment (IDE) and compiler is essential to fully optimize any MCU subsystem.

    The RISC-351 Zephyr is delivered with an innovative compiler SmartCC, the first compiler in the low-power MCU market to be based on the widely acclaimed LLVM framework. In addition to the wide compatibility of SmartCC with GCC and the latest ANSI-C standards, the compiler has been designed to maximize the use of the internal registers and thus reduce dynamic power consumption by minimizing energy consumption of the memory accesses.

    Last but not least, Dolphin Integration enables developers to go further with its new IDE SmartVisionTM, by being able to quantify the energy consumed by each function during the program execution therefore allowing a designer to identify and optimize the most energy-consuming functions.

    Article: Such a small piece of Silicon, so strategic PHY IP-smartvision.jpg


    More information on: RISC-351 Zephyr and its IDE SmartVision™