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  • eSilicon ♥ ARM!

    Article: GSA 3DIC and Cadence-esilicon-loves-arm.jpgThe things I enjoy the most at conferences are presentations by customers, the companies that solve the problems we face every day with modern semiconductor design. We all have access to the same tools and IP and use the same foundries so itís the actual design and implementation that separates the wheat from the chaff, absolutely.

    SemiWiki has direct access to dozens of customer presentations from #52DAC and will be writing about them over the summer. These types of blogs are the most viewed and the bigger the customer the more views. Or you can just mention ARM and the views go exponential because letís face it, ARM IP is in just about every design, mobile or not.

    The nice thing about eSilicon is that they are both a vendor and a customer so they have no problem talking about what they are doing and rightly so since they have taped-out hundreds of designs and shipped MILLIONS of chips so who better to listen to, especially when they talk about using ARM IP. This presentation was titled ďARM Based Designs in the Internet AgeĒ and was well worth listening to.

    eSilicon starts by using an IP hardening project to ensure the flow works well. They donít push performance here but once eSilicon engages with a customer design on a validated flow they use design virtualization to get the best possible results (performance, power, price). The example used in this presentation is a baseband processor implemented in TSMC 28nm HPL. One of the first questions you will face when you start a design is: Which of the TSMC 28nm processes will be best for my design?

    Article: GSA 3DIC and Cadence-28hpl-baseband-processor.jpg

    TSMC now has seven versions of 28nm: HP (high performance), HPM (high performance mobile), HPC (high performance computing), HPL (high performance low power), LP (low power), the recently added HPC+, which is an even faster version of HP, and ULP, which is ultra-low power for IoT and other battery powered applications. So many choices so little time, right?

    The complete presentation can be found HERE.


    Take a look at slide#3 to better understand Design Virtualization. What they are talking about here is a big data analytics system that contains a characterization of all the IP used across all the process options available. Using this technology, eSilicon can help users pick the right combination of IP, process options, operating conditions, Vt mix, etcÖ in real time by querying a data base. This essentially "virtualizes" all these choices. Users are typically stuck with their first decision on all these items because trying something new is a multi-week experiment and no one has that kind of time. Thanks to this virtualization layer, users can now try new choices and get quick feedback on the results. eSilicon can also provide an optimal set of choices for a given power, performance, or area target. They use design virtualization internally on all customer designs to make sure they deliver the best chip possible.

    Slide #5 shows where design virtualization is used early in the flow to drive the best selections and then later in the flow to continue to optimize things like memory configurations. As the implementation gets closer to tapeout more is learned about the design and therefore more optimization is possible.

    Slide #9 introduces a way for all design groups (not just eSilicon customers) to access design virtualization. It is delivered as a service. The customer provides a block that needs to be optimized and then eSilicon experts analyze and provide guidance on what to tweak to make it better. If they can't achieve the required improvement there is no charge for the service. eSilicon was founded on a success based business model and this type of design virtualization service is yet another example.