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  • Samsung: the Journey to 14nm and 10nm

    Article: Next Generation Transistors: a Tutorial from the Master-sam4-jpgAt the Samsung theatre (cutely named the Samsung Open Collaboration (SoC) theater) I watched a presentation by KK Lin on using DFM to bring up their 14nm and 10nm processes. And yes, they are real. Here is a picture I took of a 14nm wafer and a 10nm wafer. Samsung announced that they would ramp 10n to volume production by the end of next year, 2016.

    Article: Next Generation Transistors: a Tutorial from the Master-sam2-jpg

    KK explained that Samsung uses DFM in two different ways (two "faucets" as the misprint on the slides has it). Design Enablement (DE) DFM is used to fix up design mask data. This is primarily optical proximity correction (OPC) and is used since 193nm light is being used with immersion lithograph (and double patterning for some layers) to print features much less than the wavelength. However, just doing that still leaves "hot" spots on the wafer where failure is more likely if the lithography and manufacturing is not absolutely perfect.

    Article: Next Generation Transistors: a Tutorial from the Master-sam3-jpg

    So another stage of DFM is Process Enablement (PE). Obviously a lot of process monitoring is done in a completely design independent ways using various process control monitors (PCMs). But that alone doesn't get the yield ramp up fast enough for today's consumer market places especially mobile. It used to be that a ramp to volume would take a couple of years, and now it is expected within a few months of final qualification. So the PE DFM is used to do design aware process monitoring and fault analysis. It is simply not possible to look at a whole wafer in any reasonable time at a resolution that can spot problems ("looking for a golf ball in California" is one way I've heard it described) so knowing where the hot spots and failures are most likely to be found makes it tractable.

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    Article: Next Generation Transistors: a Tutorial from the Master-sam1-jpgKK's conclusion:
    • Samsung Foundry provides comprehensive closed-loop DFM solutions at both design and process level
    • During design DFM signoff tools and flows are used to prevent failures
    • For process ramp, DFM is fed forward for defect monitoring, detection and estimation
    • Samsung Foundry 14/10nm DFM are synergized to serve customers' collaborative yield learning. Not 100% sure what that means, maybe sounds better in Korean. But I think it means that by using DE and PE DFM they can ramp the leading customer designs to volume faster


    Also on the Samsung booth was a nice demonstration of how much lower power FinFET is than planar. They had two smartphones running video. In one the application processor was 28nm HKMG, and in the other it was 14nm FinFET. If you look closely at the screens on the two phones, you can see that the one on the left has a temperature of 62C and the one on the right 86C.

    Article: Next Generation Transistors: a Tutorial from the Master-samp1-jpg

    They also had continuous displays showing the instantaneous power dissipations for the two phones. At the moment that I took the pictures, the 28nm chip was disippating almost 1.5W whereas the 14nm chip was 0.8W, close the half the amount of power.
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