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  • A Key Partner in the Semiconductor Ecosystem

    Often we hear about isolated instances of excellence from various companies in the semiconductor industry which contribute significantly in building the overall ecosystem. While the individual excellence is essential, it’s rather more important how that excellence is utilized in a larger way by the industry to create a ‘value greater than the sum’.

    This is evident from ANSYS’ insightful presentations on their tools and technologies and their participation with several customers and partners in the upcoming 52nd DAC. We know about the key features of ANSYS simulation tools, such as accuracy, versatility, comprehensiveness including chip, package and system, capacity, performance, and so on that drive the design towards higher reliability and quality with faster design closure. Also, ANSYS tools’ qualification with Intel’s 14nm Tri-gate and TSMC’s 10nm FinFET and 16nm FF+ technology nodes makes them capable of solving design problems at leading edge technologies. This week when I reviewed ANSYS’ DAC agenda, I realized that ANSYS simulation technologies have become key enablers in the overall ecosystem of SoC designs. The participation of customers and partners including industry segment leaders, IP providers, foundries and design houses into ANSYS activities showcasing their simulation technologies is witness to the growing importance of ANSYS technologies in the semiconductor ecosystem.

    Article: UMC Wins Qualcomm 28nm  Second Source Contract!-ansys_dac-jpg

    In today’s SoC ecosystem where designs are exceeding a billion gates including several IP blocks for different functions, and chips being manufactured at extremely thin metals and narrow noise margins, multi-physics simulations at various levels of abstractions are essential. The simulation results need to be highly accurate at individual IP level as well as the complete SoC level. Various simulation engines are required to estimate and analyze different parameters of a design such as power, IR drop, temperature, electromigration, EMI, ESD, and so on. ANSYS has put together a set of presentations and demonstrations involving multiple tools to provide solutions to control these parameters in order to optimize the designs for best power, performance, cost and reliability. These will be presented by subject matter experts at ANSYS and co-presented along with their partners in a few cases.

    ANSYS’ presentations reflecting best practices in design development and verification include –
    • Driving low-power design with physical-aware RTL power budgeting methodology
    • Achieving faster power design closure with integrated chip-package co-analysis
    • Design-aware power grid prototyping
    • Enabling silicon success of power-efficient andreliable FinFET IP designs
    • Best practices for ensuring ESD integrity at IP and SOC using PathFinder
    • Achieving thermal-aware EM through chip-package-systempower-thermal convergence in 3DIC designs
    • Ensuring chip-aware system-level power and signal integrity analysis
    • Rethinking the Power Analysis Flow


    There are interesting customer workshops (by invitation) presented by leading semiconductor companies such as Samsung, Avago, Infineon, Freescale and others –

    Monday, June 8: Methodologies for Ensuring Timing, Reliability and Thermal Integrity

    This will include the following topics:
    • Clock Jitter Analysis Flow using RedHawk-PJX
    • Achieving Power and Reliability Sign-off for Automotive SemiconductorDesign
    • Thermal Integrity and Thermal-aware EM Reliability Check for 3DStacked Dies in Automotive Application
    • IntegratingPathFinder into a SoC ESD CAD Sign-off flow


    Tue, June 9: Accelerating IC / System Design Closure for Power and Reliability

    This will include the following topics:
    • Automated flow fortechnology/design specific power grid design
    • IR Analysis of Large ICs through DistributedMulti-processing (DMP) Technology
    • Accurate SiliconCorrelation using Chip-Package Co-analysis
    • Power Integrity Analysis ofa Combined PCB, Package and Die


    Wed, June 10: Designing for Low-Power and High-Performance SoC

    This will include the following topics:
    • Early Power Grid Prototyping Flow
    • Distributeand Conquer - Taming Power-integrity Sign-off Challenges of Gigascale Designs
    • Reference Flow and RTL Power Methodology for Energy-Efficient IP and SoCDesigns for Mobile Applications
    • Accurate and Early Power Prediction Enables Better Power Efficiency and Faster Design Closure


    Then there will be several entertainment items and industry level presentations in the open theatre at ANSYS booth #1232. Also there will be presentations focused on leading foundries and different industry segments such as IoT, automotive, and mobile at collaborated booths:

    Automotive Village, booth #1303
    ARM Connected Community, booth #2414
    TSMC OIP, booth #1933
    Samsung Electronics, booth #933.

    Check the detailed abstracts of various presentations at the ANSYS website here. Click the “presentation & demo schedule” to review abstracts and choose the best sessions according to your preferred time. Click the "registration" link to register for the sessions.


    Pawan Kumar Fangaria
    Founder & President at www.fangarias.com