WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 569
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 569
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
)
            
14173 SemiWiki Banner 800x1001
WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 569
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 569
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
)

Innovus: Cadence’s Next Generation Implementation System

Innovus: Cadence’s Next Generation Implementation System
by Paul McLellan on 03-11-2015 at 7:00 am

 Yesterday was the first day of CDNLive. There were three keynotes. The first was by Lip-Bu Tan, Cadence’s CEO (and the Chairman of Walden International that he will be the first to remind you). The most interesting tidbit was that Cadence now has over 1000 people working on IP and that it represents 11% of their revenue. Then he announced Innovus, Cadence’s next generation of physical design (much more below).

The second keynote was by Simon Segars, the CEO of ARM. He painted a vision of how the mobile phone will eventually become the only device you need, holding your plane tickets, passport, car keys, house keys, thermostat control and so on.

He also outlined how the datacenter environment is changing from simply being mobile device and huge cloud datacenter, to having intelligence distributed through the network too. Of course, Intel does not necessarily have the ideal products for this and it is a big opportunity for 64-bit ARM. Although ARM does not have the single process performance of a high end Intel processor, it has much lower power, lower cost, easy to integrate and so smaller physical size, and very high throughput due to the large number of cores possible.

 But the most interesting keynote was the third, by Anirudh Devgan, SVP of Digital and Signoff. I think that means that if it ends in “-us” then he has it in his organization. And he has one more product in his portfolio after today, Innovus. This is Cadence’s next generation physical design, rebuilt from the ground up and tied in tightly with all the already-announced analysis tools such as Tempus and Voltus. The key big picture numbers are that it is 10-20% better PPA than Encounter and 5-10X faster.

Anirudh jokingly said that when he joined Cadence, if he went to a bar people would say “Cadence is pretty good, but they need to improve their placement.” Well, Innovus has a completely new placement engine, GigaPlace and a new optimization engine, GigaOpt. There is a new advanced clcok design system based on the Azurro acquisition from a couple of years ago.

Innovus has been with initial customers for quite some time, so that now that the public announcement is here it already has success stories and a track record of results.


On run-time above are several designs. The top one is 9.3M cells in 28nm where the speedup is almost ten times, from 700 hours to 70 hours in round numbers. The last design is a mobile SoC which went from 150 hours to 29 hours (not quite scraping under the day) for a 5X speedup.


But running fast is nice, but ultimately results are what count. Power, performance, area or PPA. The above graph shows a microprocessor design (no idea whose but the previous methodology was manual which has to narrow the field quite a bit, but being 16nm not 14nm means it is not the company I first thought of). The old manual design took a long time and gradually crept closer to the goal (the hard to see blue line). With Innovus, not only was the goal reached much faster, but it was exceeded (the red line).

There are rumors around that Cadence has won Apple away from Synopsys. Of course nobody can comment on this. When I heard the rumor it made little sense since Cadence is also rumored to have lost pretty much every benchmark below 28nm with Encounter so it seemed unlikely Apple would be an anomaly. But if it is Innovus then the rumor is much more credible.

ARM have been using it with the Cortex-A72 (their new core announced a month ago). As Noel Hurley, who is general manager of the CPU group, said:At ARM, we push the limits of silicon and EDA tool technology to deliver products on tight schedules required for consumer markets. We partnered closely with Cadence to utilize the Innovus Implementation System during the development of our ARM Cortex-A72 processor. This demonstrated a 5X runtime improvement over previous projects and will deliver more than 2.6GHz performance within our area target.

Apologies for the poor quality of the images. I wasn’t given a copy of the presentations so these are all photos of the screen. But I figured getting the information out quickly is more important.

Details of Innovus are on the Cadence website already here.

Share this post via:

Comments

0 Replies to “Innovus: Cadence’s Next Generation Implementation System”

You must register or log in to view/post comments.