The subtle complexity of analog and RF circuits is now part of the SoC world, where the analog and RF design modules have to coexist with the digital component, which is discrete in nature. The SoC devices for mobile, Internet of things (IoT) and connected wearable are now made up of mixed-signal SoCs in which RF front-ends go side by side with complex digital and analog circuitry on the same chip.
However, integrating and verifying analog and RF design modules with the digital blocks is not an easy task. Apart from overcoming the design and verification challenges involved, the task now also requires efficient design data management of analog, RF and digital parts in the course of executing the SoC project. Part of that data management relates to the coherent organization of design resources such as libraries and EDA tools made available through a distributed and synchronized data system.
Data management for RF designs
In the not-so-recent past, the analog-RF parts of a design were done by separate design groups that comprised experienced design engineers developing purely analog or RF designs. With the increase in the growth of mixed-signal designs due to the emergence of new initiatives, such as IoT, wearable etc. the notion of separate, isolated groups is changing, and SoC design groups now have a number of analog, RF and digital designers exposed to a variety of EDA tools from Cadence, Synopsys, Mentor Graphics, Keysight Technologies (formerly Agilent Technologies), etc. As a result of the growing amalgamation of the analog and RF domains with the digital world, a digital IC engineer could well be working closely with, and have greater interdependencies with, analog and RF engineers.
As RF designs converge and collide with digital and analog designs, design tools must facilitate a new era of integration of analog and digital content on SoC platforms. EDA tool providers such as Cadence Designs and Keysight Technologies have already realized this and have taken the initial steps to ensure interoperability between the Virtuoso® platform and ADS, since design and simulation teams need to work together and share common libraries. With such global dynamics in place, to improve design flow efficiency, design companies find it necessary to deploy design data management tools that support all types of designs and that enable design engineers in different locations to collaborate more productively.
Some design companies have not focused too much on data management tools at an enterprise level for different types of design domains. The result has been that different designs groups within the enterprise have chosen different data management tools on an ad hoc basis more suited to a specific design type. The problem with this approach is that it results in different data repositories being created for different design groups using different tools, which quickly becomes a maintenance nightmare for the IT department. Another pitfall that design groups often fall into is the assumption that the design management software used by the software industry would work as well for the semiconductor industry. The requirements of the semiconductor industry are different, with large design databases, numerous files and complex design flows.
The challenge to deploying a uniform data management tool for all design groups typically comes from the digital team, which usually doesn’t invest in commercially-available design data management software. Most of them invest in open source software design management systems such as Subversion (primarily because it is free and uses a command-line interface) or a software-based design management software like Clearcase. The issue with open source tools such as Subversion is that, apart from poor performance when the design sites are globally dispersed, support, if needed, is extremely limited and does not have the necessary hooks (such as interfaces to EDA tools) to deal with all types of semiconductor designs.
If there is one thing that counts the most in emerging market segments such as IoT, wearable etc., it’s probably time to market. Chip designers are feeling the heat of SoC complexity on one hand and time-to-market pressures that are characteristic of the mobile and IoT markets on the other hand. That makes it imperative for chip developers to consider common data management platforms and to streamline work across the RF, analog and digital parts of the SoC design. It also becomes important for enterprises to leverage existing intellectual properties (IPs) in order to meet the time-to-market windows.
Having uniform design data management software applicable for different types of designs – RF, analog and digital -- has multiple benefits. Integration with different EDA tools facilitates design flow efficiency across the different design groups and allows all data for the entire product life cycle to be stored in repositories from the same vendor. A common data management system also facilitates easy IP reuse and makes it attractive to design companies from a cost and support standpoint.
One such data management tool, and perhaps the only tool which supports all types of design environments (RF, analog, digital and mixed-signal designs), is the SOS design data and IP management system from ClioSoft Inc. SOS enables design teams, locally or dispersed, to improve their design productivity. By ensuring tight integration with tools from different EDA companies as well the necessary hooks to ensure smooth handoffs, designers can efficiently manage their design flow methodologies. The integration of the SOS design data management platform with several design flows -- including Cadence’s Virtuoso® technology, Keysight Technologies’ Advanced Design System (ADS), Mentor Graphic’s Pyxis Custom IC Design, Synopsys’ Galaxy Custom Designer® and Laker3™ Custom Design -- allows SoC designers to invoke the data management features directly from their familiar design tools.
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Another inherent advantage of having a data management system that supports all types of designs and a number of EDA tools is that companies will not need to change the data management software if there is a change in EDA tools, thus reducing the risk of missing design timelines.
by Karim Khalfan, Director of Application Engineering, ClioSoft Inc.