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  • Altera Back to TSMC at 10nm? Xilinx Staying There

    Article: Double Patterning and Then The End of Lithography-xilinx1.jpgXilinx announced their quarterly results last week. They slightly missed their number due mainly to a decline in wireless sales. Of course Xilinx parts don't go in the smartphones since the cost and power are too high, but they are very heavily used in basestation, backhaul etc especially in China. Xilinx's business in China has been historically limited by a slower buildout to a shortage of parts (not the Xilinx parts but power amplifiers). That problem seems to have gone away and their China business is on track and the weakness is in the rest of the world.

    As always here at semiwiki it is interesting to use the FPGA market to get insight into the foundry roadmaps.

    As Moshe said on the call:
    We also achieved several important milestones for our 20-nanometer portfolio. Our Kintex UltraScale devices became the industry's first 20-nanometer FPGAs to move into volume production. Based on customer feedback, we continue to believe that we have an estimated one-year lead over the competition. This technology leadership is complemented by our Virtex UltraScale family, which is the industry’s ASIC class 20-nanometer high-end product offering. It's a very high-end of this family, we began shipping the industry’s largest FPGA which delivers over 4x of the capacity of any competitive devices.

    With regards to 16nm, they are a couple of months behind schedule. The problem is on the design end at Xilinx themselves and doesn't appear to be due to any changes on the TSMC side. Moshe said that they should tape out in May:
    Okay. So there are no issues with TSMC, they have had numerous tape outs already, they are giving us full support. The design whenever you encounter a new generation of product tends to unearth problems that you did not anticipate and as a result the closing of all of these issues is taking a little longer plus the challenges related to design for FinFET transistors are more significant. So it's not a TSMC challenge or issue at all, it's just our ability to finish the design with their support. After if you look at our business typically what sort of happens is tape it out, you get it back after a few months, you go through a lengthy evaluation cycle and then you move it into production at which point in time it takes two to three years until it reaches high volume production.

    Meanwhile Altera also had an earnings call. As you probably know they use TSMC for 20nm and above but switched to Intel 14nm (which is what TSMC calls 16nm for Chinese reasons). They are seeing a lot of the same slight weakness in end-user markets. John Daane, the CEO, said that they were also a couple of months late taping out in 14nm:
    Let me start with 14-nanometer. Our original schedule was to tape-out in first calendar quarter, we’re running a couple of months late to that and are actively working to pull that in but worst case, we will sample this fall so we are still definitely in this year.

    He also reckons that in the Intel process which has tighter pitches than TSMC that they will get a 25% area savings which is less than the original thought of 35%. But the bombshell was about 10nm:
    Question: You talked about 14-nanometer, have you guys made any decision on your foundry choice for 10-nanometer?
    We have not made that decision. We have told both, Intel and TSMC, who are working with on the technology that will likely make a decision before the end of the first calendar quarter.

    So Altera could go back to TSMC for 10nm. Of course this might all be a negotiating strategy for better wafer prices but switching to Intel for just one process generation would be unusual.

    Seeking Alpha transcripts: Xilinx and Altera

    There is a Semiwiki forum discussion on this here.