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  • WLAN Design Optimization at Lantiq

    Right now I'm typing on my MacBook Pro computer connected to the Internet through WiFi, thanks to the electronics in both my laptop and WiFi router. I kind of take WiFi for granted because it is so ubiquitous throughout my daily life, yet there are IC designers at companies like Lantiq Semiconductor that have to design and optimize for WLAN specifications like 802.11ac by designing RFIC devices. Last month at the MunEDA User Group meeting in Munich I attended a presentation by Daniel Lopez-Diaz, a senior engineer in the RF design group at Lantiq.

    Article: Not me. Who owns IP quality?-lantiq.jpg

    Related - Transistor-Level IC Design is Alive and Thriving

    Lantiq was founded over 20 years ago and has grown into a successful fabless company with 800 people, focusing on high-speed broadband, connected home, home automation and voice products. Here's the big picture showing how everything fits together:
    Article: Not me. Who owns IP quality?-we-go-beyond-chip.jpg

    They have a reference board used in WiFi router products with just a handful of highly integrated components:
    Article: Not me. Who owns IP quality?-reference-board.jpg
    EASY362 V1.1 Reference Board

    The WLAN chip supports the 802.11ac standard, operates on a 5G frequency band, and has RF bandwidths of: 20MHz, 40MHz, 80MHz and 160MHz. These requirements translate into a transmitter with a Power Spectral Density (PSD) that looks like:

    Article: Not me. Who owns IP quality?-psd-versus-frequency.jpg
    Power Spectral Density

    Related - Debugging a 10 bit SAR ADC to Improve Yield

    Another important spec is the minimum performance as the Error Vector Magnitude (EVM), also called the Relative Constellation Error (RCE) - measured in units of dB:

    Article: Not me. Who owns IP quality?-evm.jpg
    Error Vector Magnitude (EVM)

    The RFIC design team needed to verify the performance over a range of Process, Voltage and Temperature (PVT) conditions to ensure that the WLAN chip would be robust and yield well. Combinations of intra-die and inter-die variation could result in unrealistic process parameters. The approach used by the team was to create an iterative sign-off process using EDA tools from MunEDA called WiCkeD.

    Article: Not me. Who owns IP quality?-flowchart.jpg
    Iterative Design Flow

    A simplified RF block diagram is shown below with the Transmit Mixer portion highlighted for analysis.

    Article: Not me. Who owns IP quality?-simplified-rf-block-diagram.jpg
    Simplified RF Block Diagram

    The Transmit Mixer block has two main specifications:

    • Conversion Gain (CG) of -3dB, typical
    • 1 db Compression Point (P1dB) of 7 dBm, minimum

    At the first design review it was shown that the specifications were not quite met:

    InitialTT1.26V-2.22 dB10.17 dBm
    SlowSS1.2V110 C-4.18 dB10.2 dBm
    FastFF1.32V10 C-1.62 dB10.77 dBm

    Further analysis using Worst Case Distance results instead of corners for Conversion Gain and 1 db Compression Point showed:

    Fast1.32V10 C-1.63 dB12.09 dBm
    Slow1.2V10 C-4.292 dB.5705 dBm

    Engineers quickly spotted that with Worst Case Distance analysis the result for P1DB was out of spec, so it meant three possible choices:

    1. Re-center the design to meet the spec
    2. Re-size the transistors to meet the spec
    3. Relax the specifications

    Related - Transistor-level Sizing Optimization


    RF design optimization for a WLAN chip is possible by using a Worst Case Distance approach as found in the WiCkeD tool from MunEDA. Designs can be analyzed for robustness prior to tape-out.