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  • Will 3DIC Ever Be Cheap Enough for High Volume Products?

    Article: Does 14nm magically put Intel back on the lead smartphone lap?-when3d1-jpgMore news from the 3DASIP conference. Chet Palesko of SavanSys Solution had an interesting presentation with the same title as this blog (although this blog draws from several other presentations too). Chet took a look at what aspects of 3D are likely to get cheaper going forward. He took as a starting point that stuff that is not used only for 3D is probably already close to as cheap as it is going to be. For example, 3D chips involve bumping as does flip-chip. So although there may be some small amount of incremental improvement in cost, most of the improvement has already happened driven by flip chip. And, as an interesting aside, flip chip is still more expensive than wire-bond which is why it is only used for about 17% of chips. You only use flip chip if you need it for other reasons than cost (smaller package, higher performance etc).

    Another thing that I had not thought of is that 2.5D is expensive compared to true 3D. Of course you have to manufacture the interposer, which is done in a non leading edge process such as 65nm. But the TSV and bumping it requires is very costly since it is large so not many interposers-per-wafer. There are some savings since the die don't need TSVs, but they still all need bumping. Qualcomm, in particular, maintain that interposers are the wrong way to go (not that they have any 3D chips in production though). At a conference in Europe recently someone had numbers showing 2.5D was 6 times the cost of true 3D although that seems high to me (but I've not seen those numbers).

    So 3DIC is only the best choice if no other technology meets the product requirements, typically things like memory bandwidth, physical package size, ultra low power and so on. Most technologies are ones of last resort in that they are more expensive but have other advantages (embedded passives, multi-chip modules, even SoCs). A few are cheaper and thus displace the existing technology. Surface mount displaces through-hole assembly, until recently, each new process node displaced the previous one (at least for digital logic).

    Earlier Jan Vardarman had listed out the big pictures areas where improvement are needed:
    • EDA tool availability (especially pathfinding and thermal analysis)
    • Assembly: stacking of die
    • Wafer thinning and the temporary attach and debond process
    • Thermal, especially logic on memory (since hot spots may take DRAM out of spec)
    • Test methodology and the need for known-good-die (KGD) making wafer sort so much more important and costly
    • Yield of the whole process
    • Setting up the whole supply chain and who does what

    To keep it simple, let's assume a 3DIC with just two die, a bottom die and a top die. The bottom die cost drivers are TSV creation, TSV reveal (basically CMP), TSV creation yield loss, thin wafer yield loss, testing/known-good-die costs.The top die cost drivers are the RDL process cost and the wafer bumping cost. Then assembling the two die has silicon to silicon process cost, silicon to silicon yield loss, silicon to substrate and substrate cost. So which of these will have big improvement potential? See the tables below. The column on the right summarizes whether improvement is likely. Click on the tables to enlarge them.

    Article: Does 14nm magically put Intel back on the lead smartphone lap?-when3d2-jpg

    Article: Does 14nm magically put Intel back on the lead smartphone lap?-when3d3-jpg

    Article: Does 14nm magically put Intel back on the lead smartphone lap?-when3d4-jpg

    Chet looked at some alternatives but to wrap up he told us we were asking the wrong question. The right question is "Will the markets that require 3DIC grow fast enough to drive volume manufacturing?" After all, performance, power and miniaturization trends are continuing. And there will be some cost reduction for 3DIC which can open up new markets. One caveat is that the cost of 2.5D packaging (such as the Xilinx FPGA) should not be extrapolated to 3D. Even so, 3D is unlikely to ever be the cheapest solution and if you can package-on-package (like the Apple Ax chips) or fanout-wafer-level (FOWLP) you will.

    But in the same way people design SoCs if they cannot use an FPGA or do a board-level design, people will use 3D when nothing else will do. Like the memory stacks announced by Micron, Samsung and SK-Hynix, the recently announced graphics integrations by Nvidia and AMD/ATI, the Xilinx high-end FPGAs and so on. These are all (or soon will be) in production but at comparatively low volumes.

    <br> <a href=/cgi-bin/m.pl>More articles by Paul McLellan…</a>