WP_Term Object
(
    [term_id] => 24
    [name] => TSMC
    [slug] => tsmc
    [term_group] => 0
    [term_taxonomy_id] => 24
    [taxonomy] => category
    [description] => 
    [parent] => 158
    [count] => 560
    [filter] => raw
    [cat_ID] => 24
    [category_count] => 560
    [category_description] => 
    [cat_name] => TSMC
    [category_nicename] => tsmc
    [category_parent] => 158
)
            
TSMC Banner 2023
WP_Term Object
(
    [term_id] => 24
    [name] => TSMC
    [slug] => tsmc
    [term_group] => 0
    [term_taxonomy_id] => 24
    [taxonomy] => category
    [description] => 
    [parent] => 158
    [count] => 560
    [filter] => raw
    [cat_ID] => 24
    [category_count] => 560
    [category_description] => 
    [cat_name] => TSMC
    [category_nicename] => tsmc
    [category_parent] => 158
)

TSMC OIP: Registration Open

TSMC OIP: Registration Open
by Paul McLellan on 09-06-2014 at 9:00 am

 It’s that time of year again! The 4th TSMC Open Innovation Platform Ecosystem Forum is coming up on September 30th. As usual it is in the San Jose conference center. The TSMC OIP Ecosystem Forum brings together TSMC’s design ecosystem companies and their customers to share real case solutions to today’s design challenges. Success stories that illustrate best practice in TSMC’s design ecosystem will highlight the event. More than 90% of last year’s attendees last year said that the Forum helped them “better understand TSMC’s Open Innovation Platform” and that “they found it effective to hear directly from TSMC OIP member companies.”

Registration is now open.

 The schedule is as follows:

  • 8.00: registration opens
  • 9.00: welcome remarks
  • 9.20: industry overview and corporate updates
  • 9.50: TSMC and the ecosystem for innovation
  • 10.15: feature talk with ARM
  • 10.45: coffee break

Then at 11am the forum splits into 3 parallel tracks: an EDA track, an IP track and an EDA/IP/services track. There will be a break for lunch from 12pm to 1pm. Many of the presentations feature both a design partner of TSMC and an EDA or IP partner. Several of the presentations are on 16FF and 10FF, so this is an opportunity to hear about the experience of TSMC’s partners on the most advanced nodes. In particular, from 4pm until the end of the afternoon on the EDA track Cadence will be talking about various aspects of 16FF and 10FF design. Synopsys and Mentor are also presenting on aspects of 16FF.

The EDA track features presentations from:

  • AMCC/Cadence
  • Synopsys (several)
  • Qualcomm/Mentor
  • Cadence (several)
  • Mentor/TSMC
  • Mediatek/Synopsys

The IP track features presentations from:

  • Semtech/Snowbush
  • GUC
  • ARM
  • Kilopass
  • Cadence
  • CEVA
  • ARM (several)
  • Imagination
  • Synopsys

The EDA/IP/services track features presentations from:

  • GUC
  • Lorentz/Altera
  • eSilicon
  • Synopsys
  • Uniquify
  • Oracle/Mentor
  • ANSYS (Apache)
  • Analog bits
  • M31 Technology
  • Microchip SSTI

The day concludes with a social hour from 5.30pm to 6.30pm.

If you are doing design with TSMC (and its almost a case of who isn’t?), and especially if you are about to start on a 16FF design, then you should definitely plan to attend. I think the agenda contains a wealth of interesting sounding experience from design groups working right on the bleeding edge.

Full details of the agenda are here. Registration is here.

More articles by Paul McLellan…

Share this post via:

Comments

There are no comments yet.

You must register or log in to view/post comments.