You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!

  • Cadence white paper helps you selecting what come after DDR4

    The DRAM market is shaking… In 2014, analysts predict that LPDDR4 will surpass DDR4 for the first time. When releasing DDR4 standard, JEDEC has clearly stated that the industry should not expect any DDR5. Does this means that DRAM technology new development is ending with DDR4? According with Mike Howard, principal analyst at IHS iSuppli, “DDR4 for servers, laptops and mobile devices will be around for a long time as no successor is under development”, saying that "It will be the last DDR iteration". In fact, if you look at the DRAM industry, you can discover four emerging technologies, all based on 3D stacking approach, namely: HMC, HBM, Wide I/O 2 and DDR4-3S. This blog has been built by using information from various articles that you can find on Cadence web page. Let’s take a short look at these emerging technologies.

    DesignCon 2012 Trip Reports (iPad2 Giveaway)-3d-memories-stack-4-emerging-technologies.jpg

    Wide I/O 2: Supporting 3D-IC Packaging for PC and Server Applications
    The Wide I/O 2 standard, from JEDEC, is expected to reach mass production in 2015, covers high bandwidth 2.5D silicon interposer and 3D stacked die packaging for memory devices. Wide I/O 2 is designed for high-end mobile applications. The goal is to provide high bandwidth at the lowest possible power. This standard uses a significantly larger I/O pin count than LPDDRn, but at a lower frequency. Because stacking reduces interconnect length and capacitance, this result in lowest I/O power for higher bandwidth. Just note that Wide I/O 2 is still parallel protocol and that a logic die is inserted between the SoC and the stacked memory dies.

    DesignCon 2012 Trip Reports (iPad2 Giveaway)-hmc-architecture.jpg

    HMC: Breaking Barriers to Reach 400G
    HMC (Figure 4) is being developed by the Hybrid Memory Cube Consortium and is expected to be in mass production in 2014. The architecture essentially combines SerDes based, high-speed logic process technology with a stack of through-silicon-via (TSV) bonded memory die. In an example configuration (see above picture), each DRAM die is divided into 16 “cores” and then stacked. The logic base is at the bottom, with 16 different logic segments, each segment controlling the four or eight DRAMs that sit on top. This type of memory architecture supports more “DRAM I/O pins” and, therefore, more bandwidth (as high as 400G). According to the Hybrid Memory Cube Consortium, a single HMC can deliver more than 15X the performance of a DDR3 module and consume 70% less energy per bit than DDR3. So, Hybrid Memory Cube is based on ultra-high speed (10, 12.5 or 15 Gbps today, 25 Gbps for the next release) serial protocol, the memory chip maker supplying the “cube” also integrating a logic die, the customer SoC being packaged separately.

    DesignCon 2012 Trip Reports (iPad2 Giveaway)-hbm-architecture.jpg

    HBM: Emerging Standard for Graphics
    HBM (Above Figure) is another emerging memory standard defined by the JEDEC organization. HBM was developed as a revolutionary upgrade for graphics applications. Expected to be in mass production in 2015, the HBM standard applies to stacked DRAM die, and is built using TSV technologies to support bandwidth from 128GB/s to 256GB/s. JEDEC’s HBM task force is now part of the JC-42.3 Subcommittee, which continues to work to define support for up to 8-high TSV stacks of memory on a 1,024-bit wide data interface. In October 2013, the Subcommittee published JESD235: High Bandwidth Memory (HBM) DRAM, which uses wide-interface architecture to achieve high-speed, low-power operation. Please note that HBM is still parallel protocol and that a logic die is inserted between the SoC and the stacked memory dies.

    DDR4-3DS
    A lower cost, lower performance alternative 3D approach is DDR4-3DS. This standard presents an evolutionary development of the current DDR4 interface. With DDR4-3DS, a master-and-slave memory chip pair are bonded together and packaged as shown in Figure 4. Only the master die has the memory interface logic, thus reducing the load on the host controller. As a partial step towards 3D, the technology provides incremental improvement and cost efficiency, but does not achieve the breakthrough performance and power benefits of the other technologies.


    This white paper from cadence: “Five Emerging DRAM Interfaces You Should Know for Your Next Design” will certainly help you deeper your knowledge about these emerging protocols, when “3D Memory Landscape take Shape” specifically addresses the 3D related architectures.

    DesignCon 2012 Trip Reports (iPad2 Giveaway)-table.jpg

    One or several technologies will eventually replace DDR4, but DDR4 will be used doe a long time, especially because it’s the last protocol iteration. The cumulated DDR4 Memory Controller IP sales have weighted $100 million in 2013 (source IPnest) and will be in excess of several $100s million during 2014-2020. But IP vendors have to prepare the future and Cadence will have to support some if not all these emerging technologies. If you already know the bandwidth requirement, expected release date and acceptable cost per bit for your next application, the above table can help you make a first selection of the emerging memory technology to support.

    By Eric Esteve from IPNEST