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  • PCI Express 4 specification just released for PCI-SIG DevCon

    I have been alerted by a blog from Moshik Rubin from Cadence: PCI-SIG has finally released the PCIe 4.0 rev 0.3 specification for members' review, on time for the PCI-SIG developers conference last June in Santa Clara. Since the early days of PCI Express in 2005, Denali (at that time, now Cadence) has positioned the PCIe VIP as the first to be released. This aggressive positioning was a part of Denaliís success: being the first on the market greatly helps catching the first PO from customers, large IDM or smaller IP vendors. Getting fresh cash in advance helped minimizing cash investment and boost engineering and product development effort. Sounds like a winning strategy!

    Article: NFC, Why is this a big deal?-cdns-complete-pcie-solution.jpg

    If you take a look at the PCI-SIG website, you can download the conference agenda and realize that PCIe 4.0 is more than a buzz word, as several presentations were specifically dedicated to PCIe 4.0 Electrical, Card Electromechanical Specification (CEM) or Encoding and PHY Logical. You may be surprised by the number of presentations dedicated to M-PCIe, the joint specification issued by the MIPI Alliance and PCI-SIG. In fact, PCIe 4.0 is the first specification fully integrating M-PCIe (M-PCIe was an ECN of PCIe 3.0 specification). Mobile Express attractiveness is still strong within the SC industry, and the M-PCIe dedicated presentation cover an overview, MIPI M-PHY Technical Overview, Testing and Verification of M-PCIe devices and also a Holistic Approach for M-PCIe implementation!

    Article: NFC, Why is this a big deal?-m-pcie-system-level.jpg
    The Cadence M-PCIe Subsystem IP supports up to height M-PHY lanes in each direction, and has over 100 configuration features and 1500+ input parameters, to customize the subsystem to the specific needs of the application. This very wide configurability capability is directly linked with the PCI Express specification, offering an extensive set of parameters. That is, the Cadence M-PCIe Subsystem IP uses the companyís Silicon proven PCIe Controller core, and the M-PHY Physical layer.

    The logical physical layer provides an RMMI interface to connect the M-PHY device, and the Host Adaptation Layer (HAL), or optional AXI3, provides connectivity to the client. The picture below illustrates the RMMI implementation:

    Article: NFC, Why is this a big deal?-m-pcie-ip-level.jpg

    As usual, Gen-4 specification is doubling the bandwidth while keeping backward compatibility. Letís review the main changes/additions of the new specification:

    • Speed negotiation and operation at 16.0 GT/s
    • Link equalization procedure for 16.0 GT/s
    • Inferring electrical idle conditions at 16.0 GT/s
    • Reorganization of the PCI Express electrical specification
    • Incorporation of all post Gen3 ECNs (including M-PCIe)

    Cadence PCIe 4.0 VIP was announced in May and provides support for all of those changes. This VIP has been demonstrated during PCI-SIG DevCon 9 at the Santa Clara Convention Center. As mentioned earlier in this paper, Cadence has adopted the same aggressive Verification IP launch strategy for than Denali. More than just a successful marketing strategy, this policy makes Cadence as essential part of the PCI Express Ecosystem, as IP vendors and IDM need to benefit from a VIP available in advance, before the final PCIe 4.0 specification is frozen, to be able to launch PCIe 4.0 products with a TTM advantage! As far as I am concerned, I also expect to see the PCIe 4.0 Design IP to be released soon by Cadence, as the Design IP group should benefit from the efforts made by the Verification IP team!

    From Eric Esteve from IPNEST

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