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  • Is SOI Really Less Expensive?

    CES 2012 Forum Discussion Thread (iPad2 Giveaway)-fd-soi-vs-bulk.gifIntroduction
    There have been some claims made recently that planar Fully Depleted Silicon On Insulator (FDSOI) is less expensive than bulk planar processes and FinFETs at various nodes. Some of these claims suggest that FinFETs in particular are significantly more expensive. My company, IC Knowledge LLC produces the most widely used IC cost modeling software in the semiconductor industry. Recently we have developed a new version of our Strategic Cost Model that is particularly well suited for cost comparison between bulk, FDSOI (planar) and FinFETs (both on bulk and SOI). In the rest of this article I will presents some results from these comparisons.

    Assumptions
    One of the key objectives of this analysis is to make the comparison between the different process variants as direct a comparison as possible. Our model uses detailed process flows for each process and we have tailored the process flows to reflect the requirements of the different processes while keeping as many process details the same as possible. Specifically:

    • We have used an M1 half-pitch of 48nm for the 28nm node, 38nm for the 20nm node and 32nm for the 14nm node for all processes.
    • Each process has 10 metal layers with layers 1 through 4 at 1x, 5 and 6 at 2x, 7 and 8 at 4x and 9 and 10 at 8x the M1 dimension.
    • STI/Fin, gate, contact and silicide (where used) are all 1x layers (STI/Fin is 0.75x and gate is 1.3x for FinFETs).
    • All processes add local interconnect (1x layer) and MIM capacitors at 20nm.
    • All processes include mask set amortization with the same exposures per reticle.
    • All calculations are for a 300mm wafer fab running 30,000 wafers per month located in the United States. The fab is always assumed to be a new greenfield fab.
    • All processes support 3 threshold voltages.
    • All processes assume the same yield loss per mask.
    • At processes use the same multi-patterning schemes at each node.


    28nm Bulk Versus 28nm FDSOI
    The first case we examined is a 28nm bulk planar process modeled after TSMC versus a 28nm FDSOI planar process modeled after ST Micro. The following table summarizes the two processes:

    CharacteristicBulk – 28nm –“TSMC like” processFDSOI – 28nm – “ST Micro like” process
    Transistor typeBulk planarFDSOI planar
    Gate oxideGate last high-kGate first high-k
    Threshold voltages33
    Metals layers1010
    Mask layers4939
    Multi patterning masks00
    Total masks4939
    Line yield (%)97.6%98.1%
    Starting wafer cost (normalized)3%15%
    Processing cost (normalized)97%83%
    Total cost (normalized)100%98%


    The costs in the table are all normalized to the total cost of the bulk 28nm process being 100%.
    As we can see from the table, the FDSOI process has a higher starting wafer cost but a simpler process and the net final result is a slightly lower overall wafer cost.

    20nm Bulk Versus FDSOI Versus FinFET
    For the second case we looked at a 20nm bulk planar modeled after TSMC, versus a 20nm FDSOI planar process modeled after ST Micro. The following table summarizes the two processes.

    CharacteristicBulk – 20nm –“TSMC like” processFDSOI – 20nm – “ST Micro” like process
    Transistor typeBulk planarFDSOI planar
    Gate oxideGate last high-kGate first high-k
    Threshold voltages33
    Metals layers1010
    Mask layers5243
    Multi patterning masks1212
    Total masks6455
    Line yield (%)96.8%97.3%
    Starting wafer cost (normalized)2%11%
    Processing cost (normalized)98%88%
    Total cost (normalized)100%100%


    The costs in the table are all normalized to the total cost of the 20nm bulk planar being 100%.
    From the second table we can see that the cost for the bulk planar process and FDSOI process are virtually identical. The FDSOI planar process once again has a higher starting wafer cost but the simper and lower cost process offsets the starting wafer cost.

    14nm FDSOI Planar Versus FinFET on Bulk and FinFET on SOI
    For the final case we will look at a 14nm FDSOI Planar process modeled after the ST Micro process and compare it to a FinFET on bulk process modeled after TSMC and a FinFET on SOI process modeled after IBM. The following table summarizes the three processes.

    CharacteristicFDSOI – 14nm – “ST Micro” like processFinFET on bulk – 14nm – “TSMC like” processFinFET on SOI – 14nm – “IBM like” process
    Transistor typeFDSOI planarFinFET on bulkFinFET on SOI
    Gate oxideGate first high-kGate last high-kGate first high-k
    Threshold voltages333
    Metals layers101010
    Mask layers454448
    Multi patterning masks131211
    Total masks585659
    Line yield (%)97.1%97.1%97.0%
    Starting wafer cost (normalized)11%2%10%
    Processing cost (normalized)95%98%87%
    Total cost (normalized)106%100%97%


    The costs in this table are all normalized to bulk FinFET total cost being 100%. From the third table we can see that when the same assumption set is used across all processes, FinFETs on bulk are 6% less expensive than planar FDSOI and 3% more expensive than FinFETs on SOI.

    Discussion
    At both 28nm and 20nm we find that planar FDSOI is roughly comparable to bulk planar processes in cost. In both cases planar FDSOI should produce a significant advantage over bulk planar in performance and or power consumption making planar FDSOI a very attractive option for 28nm and 20nm.

    At 14nm we find that when making comparable yield assumptions for planar FDSOI and FinFETs on both bulk and SOI, that FinFETs are the least expensive process although only by a small amount. The current results are in contrast to some previous work that found FinFETs to be significantly more expensive than planar FDSOI at the same node. We believe the key driver of the differences in results is very unfavorable yield assumptions for FinFET processing used in the previous work. We furthermore believe that mature FinFET process yields have already been achieved by Intel and will soon be achieved by others and that such process yields will be in the high ninety percent range making yield a non-differentiating factor between the processes.

    To-date, the majority of the logic producers have chosen FinFETs on bulk for the 14nm (16nm for TSMC) generation. From this analysis it does not appear that cost is a significant differentiator between these three process options. IBM is the only company known to be pursuing FinFETs on SOI at 14nm driven by IBM’s embedded DRAM on SOI technology. Once again cost is not a differentiator based on this work.

    Conclusion
    Using the same yield per mask layer assumptions for both planar FDSOI and FinFETs it has been shown that the costs for planar FDSOI and FinFETs on bulk or SOI are all comparable at the 14nm node. Decisions on which process to pursue are therefore expected to be driven by factors other than cost.