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  • Webinar: Making Design Reuse Work

    Please join me for an IP conversation in collaboration with ClioSoft on Wednesday, April 30th, 2014 @ 11:00 AM PST. At the EDPS Workshop IP day there were two interesting presentations on IP reuse. The first one was by Warren Savage of IPextreme: Top Ten Reasons Why Internal IP Reuse Fails. The second was by Ranjit Adhikary of ClioSoft: Making Design Reuse Work. Take a look at the slides and let’s talk about it.
    Article: Why AMD is Up Q4, While Intel is Down-cliosoft-diagram-jpg
    Topic: Making Design Reuse Work
    When: Wednesday, April 30th, 2014 @ 11:00 AM Pacific
    Presenter: Daniel Nenni, SemiWiki

    Register for the Web Seminar

    Who should attend


    • Managers and engineers using IP's in their SoC
    • CAD engineers/managers

    Overview
    Design Reuse and IP Management are common buzz words in our industry. Yet of late, they have gained more significance with a number of companies emphasizing the need to reuse designs as much as possible.

    In order to make design reuse work a number of things must be considered: Selecting the desired IP and integrating it into the design while simultaneously managing the updates to the IP is one aspect of the design flow which must be fine-tuned. It is also necessary to increase the participation of designers in creating reusable IP and provide a forum through which designers can collaborate. Finally, to further the cause of design reuse, it is important for us to move away from the traditional IP model and identify other things in the design flow which can be considered as IP. In this presentation, we will focus on how we can make design reuse work more productive.

    About the Presenter
    Daniel Nenni has worked in the Silicon Valley for the past 30 years with computer manufacturers, electronic design automation (EDA) software and semiconductor IP companies. Currently Daniel is a Strategic Foundry Relationship Expert for companies wishing to partner with TSMC, UMC, SMIC, GLOBALFOUNDRIES, Samsung, and their top customers. Daniel's latest passion is the Semiconductor Wiki project (www.SemiWiki.com).

    How to Attend
    The seminar will be conducted via WebEx meeting service. A web URL to join the meeting will be emailed a day before the seminar. The WebEx meeting application will automatically be downloaded when you click on the URL on the day of the seminar.

    Register for the Web Seminar

    About ClioSoft, Inc.
    ClioSoft is the premier developer of hardware configuration management (HCM) solutions. The company's SOS Design Collaboration platform is built from the ground up to handle the requirements of hardware design flows. The SOS platform provides a sophisticated multi-site development environment that enables global team collaboration, design and IP reuse, and efficient management of design data from concept through tape-out. Custom engineered adaptors seamlessly integrate SOS with leading design flows - Agilent's Advanced Design System (ADS), Cadence's Virtuoso® Custom IC, Mentor's Pyxis Custom IC Design, Synopsys' Galaxy Custom Designer and Laker™ Custom Design. The Visual Design Diff (VDD) engine enables designers to easily identify changes between two versions of a schematic or layout or the entire design hierarchy below by graphically highlighting the differences directly in the editors.

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    Article: Why AMD is Up Q4, While Intel is Down-fablessbanner2-jpg