The first leg is that Cadence has new adaptable interconnect performance characterization test suite in the Cadence Interconnect Workbench, along with AMBA Designer integration, that delivers a significant speed-up of performance analysis and verification of CoreLink CCI-400 system IP and NIC-400 design tool based systems.
The second leg of the stool is that Cadence now provides ARM Fast Models combined with the Palladium XP II platform to support ARMv8-based system embedded OS verification. What this means in practice is that it is much easier to use Cadence's hybrid virtual platform technology using ARM Fast Models for the processor (and perhaps some peripherals) and Palladium emulation to model the parts of the design that only exist at RTL. In particular, operating system (OS) bringup should be straightforward since everything is coming from a single supplier, Cadence.
Thirdly, verification IP (VIP) supporting the ARM AMBA5 CHI protocol for advanced networking, storage and server systems is now available for simulation and the Palladium XP II platform.
Together these three capabilities make bringing up ARM Cortex based systems easier. The lead customer for this is nVidia. As Kevin Kranzusch, vice president, System Software says:
The Cadence Palladium solution for embedded software development enabled by ARM-based Fast Models helps us reduce the system software validation cycle and ensures a smoother post-silicon bring-up.
I worked for several years in the virtual platform market, as did Frank Schirrmeister who I met to discuss the announcement. The big problem with virtual platform technology was never the processor modeling, which was amazing technology, but modeling the boring peripherals. No matter how good the modeling technology, it took time and money to create and maintain the models. Since we were selling the ability to start software development earlier, taking time reduced the value proposition, and taking money is always worse than not needing to. It is starting to look really important that the emulation has transformed from something esoteric that the occasional development group had for SoC design, into something mainstream that is part of every verification strategy. The result is that hybrid virtual platforms with processors modeled using the JIT compiler technology and peripherals modeled using RTL on an emulator is the "killer app" for virtual platforms.
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