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  • Why SOI is the Future Technology of Semiconductor

    No doubt that FDSOI generate high interest these days and I found a very interesting contribution from Zvi Or-Bach, President and CEO of MonolithIC 3D, Inc. Zvi has accepted to share his wrap-up from IEDM, in a blog for Semiwiki readers. If you remember the long discussion we had in Semiwiki about cost comparison, some comments were posted by people deploring that the source of the cost related data was unique. Thanks to Zvi, we have now multiple sources, from GlobalFoundries to IBS, addressing cost comparison at technology level, wafer level and finally 20nm die cost comparison at 100 mm2 and 200 mm2. This blog is excellent, and very complementary with the paper from IEDM discussed last week in Semiwiki. My comments in purple, the dark text from Zvi Or-Bach, the original blog is posted below (you also can find it here ):

    Let’s start with the short answer - because:

    A. SOI is cheaper to fabricate than FinFet with comparable performance, and it is easier and cheaper to build FinFet on SOI which then provides better performance.

    B. SOI is the natural technology for monolithic 3D IC for all overlaying transistor layers, and monolithic 3D is the most effective path to keep Moore's Law

    C. SOI, or better 'XOI', is the most efficient path for most of the new concepts such as alternate materials for transistor construction and other structures like nano-wires.

    Let’s now elaborate and discuss each of these points.

    Starting with A: The following chart from Globalfoundries was presented on June 2013 at the FD-SOI Workshop, Kyoto, Japan. The chart illustrates that the best cost per transistor is the classic polysilcon gate at the 28nm node, that FD-SOI is cheaper than bulk with comparable performance at 28nm HKMG, and that FD-SOI at 20nm is cheaper than 14nm FinFet at the same performance level.
    Article: How ST-Ericsson Improved DFM Closure using SmartFill-globalf-cost-compar.jpg

    Similar information was presented by IBS (International Business Strategies), in Oct 2013 at the SOI Summit Shanghai, China.

    Article: How ST-Ericsson Improved DFM Closure using SmartFill-cost-comparison-ibs.jpg


    And before that D. Handel Jones of IBS in a 2012 White Paper presented the following table.


    Article: How ST-Ericsson Improved DFM Closure using SmartFill-fdsoi-die-cost-20nm.jpg

    Clearly the SOI substrate costs much more than the bulk substrate ($500 vs. $120), but the improvement in performance and the reduction of cost associated with FD processing neutralizes the substrate costs and makes the SOI route far more attractive. The following charts were included in a Comparison Study of FinFET on SOI vs. Bulk done by IBM, IMEC, SOITEC and Freescale:
    Article: How ST-Ericsson Improved DFM Closure using SmartFill-parasitics.jpg
    Article: How ST-Ericsson Improved DFM Closure using SmartFill-variability.jpg

    For the second point "B, SOI is the natural technology for monolithic 3D", in monolithic 3D the upper semiconductor layer is very thin (<100nm) and is placed over oxide to isolate it from the interconnection structure underneath - hence SOI.

    In this month’s IEDM 2013 two papers (9.3, 29.6) presented exciting demonstrations of monolithic 3D IC. It is interesting to note that Prof. Emeritus Chenming Hu of Berkeley (past TSMC CTO) who is now very famous due to his pioneering work on FinFets, is a co-author of these two pioneering works on monolithic 3D IC. The following figures illustrate the natural SOI structure of the upper transistor layers:


    Article: How ST-Ericsson Improved DFM Closure using SmartFill-tsv-multilayered.jpg



    Article: How ST-Ericsson Improved DFM Closure using SmartFill-flow.jpg



    Article: How ST-Ericsson Improved DFM Closure using SmartFill-3d-integration.jpg


    In his invited paper at IEDM 2013 Geoffrey Yeap, VP of Technology at Qualcomm, articulates why monolithic 3D is most effective path for the semiconductor future: " Monolithic 3D (M3D) is an emerging integration technology poised to reduce the gap significantly between transistors and interconnect delays to extend the semiconductor roadmap way beyond the 2D scaling trajectory predicted by Moore’s Law." As illustrated by his Fig. below.

    Article: How ST-Ericsson Improved DFM Closure using SmartFill-beol-parasitics.jpg

    Clearly dimensional scaling is not providing transistor cost reduction beyond the 28 nm node, and the large fabless companies--Qualcomm, Broadcom, Nvidia, and AMD—recently reported this fact once again. The industry is trying to accommodate this new reality, while still rushing to develop and adopt more advanced nodes at escalating costs and complexity. And it is encouraging to see that Qualcomm are actually 'putting their money where their mouth is" as CEA Leti just recently announced an agreement with Qualcomm to Evaluate Leti’s Non-TSV 3D Process. Thus it was natural for Leti to include in their presentation at their promotional event in conjunction with this year’s IEDM 2013, slides advocating monolithic 3D as an alternative to dimensional scaling.
    Article: How ST-Ericsson Improved DFM Closure using SmartFill-leti.jpg

    Leti’s presentation goes even further...as well as MonolithIC 3D blog, you will find the last part here

    Above data compiled by Eric Esteve from IPNEST