WP_Term Object
(
    [term_id] => 121
    [name] => IROC Technologies
    [slug] => iroc-technologies
    [term_group] => 0
    [term_taxonomy_id] => 121
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 16
    [filter] => raw
    [cat_ID] => 121
    [category_count] => 16
    [category_description] => 
    [cat_name] => IROC Technologies
    [category_nicename] => iroc-technologies
    [category_parent] => 157
)
            
banner2
WP_Term Object
(
    [term_id] => 121
    [name] => IROC Technologies
    [slug] => iroc-technologies
    [term_group] => 0
    [term_taxonomy_id] => 121
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 16
    [filter] => raw
    [cat_ID] => 121
    [category_count] => 16
    [category_description] => 
    [cat_name] => IROC Technologies
    [category_nicename] => iroc-technologies
    [category_parent] => 157
)

How Resistant to Neutrons Are Your Storage Elements?

How Resistant to Neutrons Are Your Storage Elements?
by Paul McLellan on 08-13-2013 at 1:01 pm

There are two ways to see how resistant your designs are to single-event errors (SEE). One is to take the chip or even the entire system and put it in a neutron beam and measure how many problems occur in this extreme environment. While that may be a necessary part of qualification in some very high reliability situations, it is also too late in the design cycle in most circumstances. What is needed is software to estimate the reliability during design when there is still time to do something about it.

iRoc has two tools for doing this. TFIT is used to evaluate individual cells such as flip-flops and memory elements and assess their failure rate known as FIT (failure in time). The second program, SoCFIT is used at the chip level once TFIT has been used on all the cells. It works out the FIT for the entire design based on how the various cells have been connected. A neutron that misses a flop may still cause a problem if it hits a cell connected to the flop and the current spike causes the storage element to change its value.


iRoc have just released TFIT 3.0, the latest version of the cell-level analysis tool with some major changes:

  • the necessary design layout parameters are automatically extracted from the cell layout
  • the temperature of the device may now be set to be taken into account during soft error effect simulation
  • it can analyze a named cell in the middle of a design without it having to be moved to a separate file
  • output can now be exported in xml format file which can later be used by SoCFIT or by other analysis programs


Most SoC designers do not create their own cell libraries and so they are unlikely to use TFIT directly themselves. TFIT is intended to be used by library and memory designers so that they can create libraries with acceptable reliability. Note that it is not possible to design a library so it is completely immune to SEE but what is important is to create a library with fairly uniform FIT scores. Like building a chain, you want all the links to have roughly the same strength. A cell with an especially good FIT is like an extra-strong link in the chain, it is probably a waste of resources since it is the weakest links that determine the strength of the chain just as it is the cells with the poorest FIT scores that it makes sense to focus on improving to improve the reliability of the library.

Share this post via:

Comments

There are no comments yet.

You must register or log in to view/post comments.