WP_Term Object
(
    [term_id] => 35
    [name] => Perforce
    [slug] => perforce
    [term_group] => 0
    [term_taxonomy_id] => 35
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 96
    [filter] => raw
    [cat_ID] => 35
    [category_count] => 96
    [category_description] => 
    [cat_name] => Perforce
    [category_nicename] => perforce
    [category_parent] => 157
)
            
image ad semiwiki helix iplm ip centric design 800x100 (3)
WP_Term Object
(
    [term_id] => 35
    [name] => Perforce
    [slug] => perforce
    [term_group] => 0
    [term_taxonomy_id] => 35
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 96
    [filter] => raw
    [cat_ID] => 35
    [category_count] => 96
    [category_description] => 
    [cat_name] => Perforce
    [category_nicename] => perforce
    [category_parent] => 157
)

Design Test and Regression Management of SoCs

Design Test and Regression Management of SoCs
by Daniel Payne on 06-28-2013 at 2:26 pm

Eric Peersfounded Missing Link tools in 2008 and his company was acquiredby Methodics in 2012, so I met with him at DAC to understand how their EDA tools for Design, Test and Regression Management are used in an SoC design.


Eric Peers, Methodics

Q: What do Methodic tools do?

They help you to validate your chip for semi conductor companies.
Evolve has been the product name for years

Merger: tests and regressions, test that all the files are correct, everyone on the team knows where we are at on the test plan. Applying tests seemlessly throughout the design team, the server catches any error on the changes that have been made.

Analog Smoke Test is new for this year and is part of VersIC.
Data Management and Design Management combined with Verification.

Q: Who are using your tools?

– Companies using: Tier 1 industry, semi, cpu.
– Licensed per user, annual fee. Runs on your design environment, mostly Linux.

Q: How do your tools help me during design?

UVM – Focus of how you verify a chip within an HDL like SystemVerilog to get complete coverage. Front-end RTL focus. Generates a lot of verification data, but how do you organize it? Lots of tests quickly with minimal effort. Evolve methodology complements UVM results.

Q: How has DAC been for you this year?

DAC – Wow, analog smokes is something new and important. This is a unified way to show my front end and back end designers. Both of our suites are filled, and we are at capacity. Ad hoc, internal tools have not met the needs.

Q: If I wanted to evaluate your tools, what does that process look like?

Evaluations – normally a few months to 6 months, based on the size of the design team.

If the design team has no DM experience, then they can evaluate within days to weeks. Internal DM tools are expensive to maintain and extend. Easier to buy something production proven, versus internal systems.

Q: What other trade shows does Methodics attend?

Other trade shows – CDN Live, DVCON.

Q: Which 3rd party programs are you part of?

3rd party – Cadence (#1 for analog), Synopsys. Digital side – anyone, SImulator agnostic.

*lang: en_US

Share this post via:

Comments

There are no comments yet.

You must register or log in to view/post comments.