by Matthew Hogan, Mentor Graphics
At all process nodes, countless hours are diligently expended to ensure that our integrated circuit (IC) designs will function in the way we intended, can be manufactured with satisfactory yields, and are delivered in a timely fashion while meeting the market need. Traditional IC verification relies on a collection of well-known and well-understood tools. Design rule checking (DRC), layout vs. schematic comparison (LVS), electrical rule checking (ERC), parasitic extraction (PEX), design for manufacturing (DFM) and simulation (most often SPICE and timing closure) are all used as part of this cohesive verification flow that provides us the insight required to find and correct any errors or omissions in our design process. Many design errors lead to hard failures in manufacturing, and can be readily identified and fixed, like a metal width that is too small for a process node layer, cells that were incorrectly placed, or shorts across other elements in the design. Finding and fixing these issues is the mainstay of IC verification.
The legacy of simulation
SPICE simulation, and the associated parasitic extraction that it uses, plays a vital role in identifying less obvious errors—those that deal primarily with reliability. Ensuring that you have the correct simulation vectors to provide sufficient coverage while validating the waveforms or analyzing messages from your simulation environment can be time-consuming and CPU-intensive activities, where results often require both expert interpretation and the keen eye of someone who understands the subtleties of each particular design.
Finding scalable alternatives
Whichever Greek philosopher first said that necessity is the mother of invention must have foreseen the challenges that the IC industry would one day face. Time and again, when faced with a new set of requirements not addressed by existing tools, engineers have leveraged their imaginations to create innovative solutions, designs, and process flows.
The same is true for reliability verification. With larger designs, smaller process nodes, and the increased pressure on time-to-market schedules and productivity targets, many design teams are turning to new alternatives that provide critical advantages over existing tools:
- a simple-to-use environment for the designer and verification engineer,
- fast runtime (that can scale to the full chip),
- a cohesive platform that is able to validate a wide range of issues
One tool that has found a strong role in reliability verification is Calibre® PERC™. With its ability to evaluate both the logical intent and physical implementation of the design, Calibre PERC provides a unique and powerful reliability verification platform not previously available. While there are many applications where Calibre PERC technology is successfully leveraged, one of the most common uses is the automated identification and resolution of typical reliability design challenges:
- Electrostatic discharge (ESD)
- Electrical overstress (EOS) and power intent
- Voltage-aware DRC
Many of these topics may be quite familiar to you, or perhaps you already have solutions in place today to help with these issues, but let's go through them one at a time to provide a broader understanding for all.
Designers have always needed to ensure that designs are robust from an ESD perspective. To provide that surety, they need to know what structures the design requires to protect pins from an ESD event, and they need to make sure that the implementation of those structures is correct. They also need to verify that the design complies with the topology rules (that is, the correct combination of protection devices are in place), and that these devices are robust enough to handle the ESD event.
Topology rules exist to help the designer verify that the layout correctly implements the design intent. For example, do you have robust ESD structures in place (primary and secondary) to protect the pins? Are there anti-parallel (back-to-back) diodes in place for multiple power domain designs? Do you have level shifters in place for signals? Are the metal widths sufficient? Are there enough vias?
Point-to-point and current density simulations ensure metal lines and vias are sufficiently robust to handle the expected energy, should an ESD event occur. However, these types of issues are difficult to identify using traditional simulation technologies.
Generalized ESD cells are often designed for this use, but the designer must still ensure that the cell is placed correctly into the design. Additionally, the chip design may change after the ESD IP is placed, requiring the designer to adjust the ESD IP to ensure it fits within the new design parameters (area, performance, etc.). In these situations, it is essential to validate the philosophy of the ESD intent, not just check that the ESD IP has remained intact and unchanged. ESD specialists are often called upon to provide custom solutions for each design, while keeping an eye out for known issues and previous concerns. The best IP in the world can be compromised by a simple implementation oversight.
While never an ideal solution, many designers have always relied on visual inspection and manual methods to evaluate the accuracy of the implementation of ESD structures. The large number of pin pairs in today’s devices make this solution a daunting, if not impossible, task. The designer simply can’t select a “typical” connection and evaluate just a few; rather, every reasonable combination must be evaluated. This challenge was one of the catalysts that led to a rethinking of how ESD structures are evaluated.
Calibre PERC can automatically select and analyze all of the required combinations. For schematic checking, the rules are directed more towards verifying the presence of the appropriate protection schemes from a topological perspective. Users can perform checks on circuitry directly connected to pads, as well as checks on the ESD network. For layout checking, the rules focus on verifying the point-to-point parasitic resistance between the pad and the ESD device, checking current density between pad and the ESD device, detecting pmos/nmos devices sharing the same well, detecting pmos/nmos field oxide parasitics, detecting latch-up issues, and more.
EOS and power intent
Designs that incorporate multiple power domain checks are particularly susceptible to subtle design errors. Often, these subtle errors don’t result in immediate part failure, but performance degradation over time. Effects such as Negative Bias Temperature Instability (NBTI) can lead to the threshold voltage of the PMOS transistors increasing over time, resulting in reduced switching speeds for logic gates, and Hot Carrier Injection (HCI), which alters the threshold voltage of NMOS devices over time. Soft breakdown (SBD) also contributes as a time-dependent failure mechanism, contributing to the degradation effects of gate oxide breakdown.
Transistor-level power intent verification is a critical need, especially in designs that make extensive use of IP. The IP must be hooked up correctly within the design. Thin oxide gates and high power applications require tight controls for voltage and power domains. Many of these issues are difficult to identify in the simulation space or with traditional PV techniques.
Power-aware checking requires the ability to use the design’s netlist to recognize specific circuit topologies, such as level shifters, I/O drivers, and other structures, and then relate those to the corresponding GDS geometries that make up the layout, to verify that those specific elements have been included and have been implemented correctly. Unlike the foundry DRC decks, the definition of these checks do not all come from the foundry, but must be tailored to the specific design styles and practices of the designer’s company, so any tool performing this function must be highly flexible and easily programmable. A transistor-level power-aware checking tool must also be able to statically propagate voltage values from the various supplies to every node in the circuit to facilitate a variety of EOS checks.
For example, one common problem for designers trying to debug power violations at the transistor level with simplistic tools is a lack of knowledge of the intention (the functionality) of the circuit where the violation is found. Simply checking for transistors connected to multiple domains results in a large number of false errors at the boundary between domains, where level shifter structures intentionally include transistors exposed to both low and high voltages. A power-aware checking tool like Calibre PERC can prevent such false errors by using an automated circuit recognition technique to identify particular topologies. The circuit recognition functionality within Calibre PERC uses the SPICE syntax as an easy way to define complex circuit structures. Whenever power violations are detected in enable-LS, NAND or NOR structures, false errors can be quickly waived using topological recognition.
Additionally, the unified power format (UPF) provides a way to annotate a design with power intent that is independent of any hardware description language (HDL). It is typically used at all levels of the design flow. A UPF specification at the register transfer logic (RTL) level defines the power architecture of a given design, and drives synthesis and place-and-route to achieve correct implementation. In automated reliability verification, using the same UPF specification for transistor level physical verification ensures the original power intent is preserved with the final implementation.
UPF specifications can be leveraged as an integral part of Calibre PERC’s understanding of power intent. Along with the design layout data and verification rule deck, Calibre PERC examines the UPF definitions of supply networks (consisting of power switches, supply ports, and supply nets) and checks each supply port’s supply states and its connected supply net. Most importantly, it analyzes the power state tables defined in terms of these states to ensure it captures the legal combinations of supply voltages in the entire design. With integrated support for UPF, Calibre PERC can automatically assign voltages based on a design’s power intent, greatly improving verification coverage and robustness.
For smaller process nodes and high reliability designs, the spacing requirements between nets vary as the nets traverse through the design. The required spacings are dependent on the operating voltage ranges, and devices operating at different voltages must be properly protected. For example, many designs have high voltage areas, such as flash memories, that are particularly susceptible. Designers must identify vulnerable nets and devices, and perform the appropriate spacing and guarding checks on the layout. With traditional verification methods, this means creating physical layout markers to perform voltage-aware DRC.
Using its novel circuit topology-aware voltage propagation capability, Calibre PERC can automatically perform voltage analysis and apply the results against the schematic or extracted layout netlist. Target nets and devices for the voltage-aware DRC checks are selected from the layout through the direct integration of netlist-based voltage analysis, using either vectored or vectorless static voltage propagation. The voltage-aware DRC rules are then applied to the selected layout objects. Such analysis and verification is used to identify areas of the design at risk for time dependent dielectric breakdown (TDDB).
Robust reliability verification is available today as a comprehensive solution. Verification tools such as Calibre PERC include specific technologies to make fast, automated reliability verification practical. With a reliability verification methodology comprising a single tool with a unified rule deck and integrated debug environment, Calibre PERC helps designers find subtle design optimization opportunities without SPICE circuit simulation, while also enabling them to achieve the accurate and comprehensive verification necessary to ensure a repeatable and reliable design.
- Muhammad, M.; Gauthier, R.; Junjun Li; Ginawi, A.; Montstream, J.; Mitra, S.; Chatty, K.; Joshi, A.; Henderson, K.; Palmer, N.; Hulse, B., "An ESD design automation framework and tool flow for nano-scale CMOS technologies," Electrical Overstress/ Electrostatic Discharge Symposium (EOS/ESD), 2010 32nd , vol., no., pp.1-6, 3-8 Oct. 2010
Going to DAC and interested in learning more about Calibre PERC? Matt will be presenting on reliability verification several times at the Mentor Graphics booth (#2046):
- Monday, 2:00-3:00 (Comprehensive Circuit Reliability with Calibre PERC)
- Tuesday, 2:00-3:00 (Advanced Circuit Reliability with TowerJazz; complements lunch seminar)
- Wednesday, 10:00-11:00 (Comprehensive Circuit Reliability with Calibre PERC)
Registration is required for booth presentations: sign up here
Matt will also be participating in a panel on Monday from 3:00-4:00 in the front of the Mentor booth:
Achieving IC Reliability in High Growth Markets
No registration is required for panels - simply show up, listen, and learn! The panel will be followed immediately by Mentor's complimentary Happy Hour, where you'll have a chance to enjoy an adult beverage, and engage with Matt and other Mentor experts in a relaxed environment.
Matthew Hogan is a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, with over 15 years of design and field experience. He is actively working with customers who have an interest in Calibre PERC. Matthew is an active member of the ESD Association—involved with the EDA working group, the Symposium technical program committee, and the IEW management committee. Matthew is also a Senior Member of IEEE, and a member of ACM. He holds a B. Eng. from the Royal Melbourne Institute of Technology, and an MBA from Marylhurst University. Matthew can be reached at firstname.lastname@example.org