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  • SemiWiki Top 10 Must See @ #50DAC List!

    Article: Formal Verification for Post-silicon Debug-semiwiki-logo-jpg
    This list was compiled by the SemiWiki bloggers highlighting emerging technologies that we have written about and that will be demonstrated at the Design Automation Conference next week. We highly recommend you investigate them further during your time in Austin and please let us know what you think.

    Today SemiWiki has more than 35 subscribing companies that we work closely with on white papers, webinars, seminars, conferences, strategic marketing, branding, and a variety of other consulting activities. It certainly has been a mind expanding experience for us all.

    According to Google Analytics 610,946 people (IP addresses) have visited SemiWiki since going live in January of 2011. SemiWiki is built on a relational database so we can do data mining in regards to key search terms, trending topics, and demographics. This is all driven by the original content posted on SemiWiki. According to our internal analytics there are 8,582 posts by SemiWiki bloggers and registered members. 934 of those posts are from me. Wow! I need to get a life!

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    Based on all of the above here is the SemiWiki top ten list:

    1. iDRM from Sage DA. iDRM is a technology that I have worked on for the past 3 years including joint development activities with the foundries and top fabless semiconductor companies. Sign up for a DAC demo here.
    2. ACE and AFS Mega from Berkeley Design Automation. BDA’s customer list includes the top semiconductor companies and foundries all of which helped drive this new product development (I work with BDA as the foundry liaison). Sign up for a DAC demo here.
    3. High Sigma Monte Carlo from Solido. You can sign-up for the DAC tutorial (featuring me): Winning in Monte Carlo: Managing Simulations Under Variability and Reliability here, or sign-up for a Solido DAC demo here.
    4. Tempus from Cadence. Funny story: John Cooley claims to have scooped everyone on this new product announcement even though information about Tempus was sent to us the prior week. Paul McLellan was briefed at Cadence HQ but was asked not to publish until announcement day. Other credible news sources got the embargoed press release days before the announcement as well.
    5. Floorplan Compiler from Oasys. At the recent EDA Consortium Annual CEO Forecast and Industry Vision event members were asked to vote for the “Hottest EDA Startup”. The vendor receiving the most votes was Oasys Design Systems. I have heard great things about this product from customers and ecosystem partners alike. Request a demo at DAC here.
    6. SoS by Cliosoft. This is the only DM platform integrated with all major analog and custom IC design flows and the most talked about tool by customers on SemiWiki. Request a DAC demo here.
    7. Timing Explorer from ICScape. This is the only timing ECO closure solution that is placement and routing aware and is able to cut the timing closure phase in half, typically within 2-4 iterations. Request a DAC demo here.
    8. PathFinder from Apache. ESD (electrostatic discharge) is a top trending topic on SemiWiki right now. Request a DAC demo here.
    9. VersIC from Methodics is the first complete verification management system I have seen for analog design. Request a DAC demo here.
    10. Anything FinFET, which is probably the most intriguing technology we will see this decade!

    And don't forget the all important IPL Dinner:

    iPDKs: A Thriving PDK Standard

    Tuesday, June 4, 2013
    6:00 p.m. to 7:30 p.m.
    Austin Hilton Hotel, Grand Ballroom G

    Foundry support for interoperable PDKs (iPDKs) continues to grow. As of 2012, 4 of the top 5 semiconductor pure-play foundries have joined the IPL Alliance, and all the top 5 foundries have provided customers with iPDKs. iPDKs benefit the entire custom design ecosystem. Semiconductor foundries and IDMs create iPDKs to reduce their PDK development, validation, support and distribution costs while enabling advanced design flows and multiple EDA tool support. Chip designers now enjoy access to best-in-class tools, interoperable flows, and improved productivity.

    At the 7th Annual IPL Luncheon, IPL Alliance presenters will highlight the benefits of the iPDK standard and their experiences in developing and deploying foundry iPDKs. The IPL Alliance will also present an update on current and future projects as well as collaboration with other industry initiatives.


    Agenda:

    6:00 pm – 6:10 pmComplimentary dinner
    6:10 pm – 6:15 pmIntroductions - IPL update and roadmap
    6:15 pm – 6:30 pmiPDK advantages – Foundry perspective
    6:30 pm – 6:45 pmiPDK Benefits – Customer perspective
    6:45 pm – 7:00 pmiPDK and AMS Reference Flows
    7:00 pm – 7:15 pmiPDK and OPDK
    7:15 pm – 7:30 pmQ&A






    Register Now!

    Attendance at this event is free, but registration is required. Seating is limited, so reserve your seat early.



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