iDRM brings automation, ease-of-use, clarity and closure to design rules
Santa Clara, California - May 6, 2013 - Sage Design Automation (Sage-DA) has been founded to develop technology and products that automate the rule-based design and verification paradigm. Sage-DA was founded with initial investment from venture capital and angel investors including Alex Shubat, PhD, former President and CEO of Virage Logic (NASDAQ: VIRL, acquired by Synopsys in 2010) and Michael Burstein, PhD, EDA veteran and co-founder of multiple EDA companies. Coby Zelnik, former CEO of Sagantec leads the company as President and CEO.
The dire need for automation
Until today, design rule check (DRC) decks, the programs that check if IC physical designs can be manufactured, have been programmed manually with no way to verify their correctness and accuracy. In latest process technologies (20nm and below), design rules have become very complex, their description is often ambiguous and hard to understand and their respective check deck implementation can have more than 100,000 lines of code that take as long as two years to develop and debug. Manually coding these checks is therefore not only very slow, but it is also error prone, putting at risk early designs in new process technology, and potentially causing low yield, silicon failures, design re-spins and time-to-market delays.
Sage-DA is introducing its iDRM: (integrated design rule management) product, which is based on a new and revolutionary technology that enables quick graphical capture of complex design rules with instantaneous check capability that allows verification of the rule definition against test layout. iDRM provides a clear visual and unambiguous rule description for designers and at the same time enables closure between original rule intent and its DRC implementation.
Fig. 1 iDRM: Quick, clear and visual design rule capture with instantaneous rule check
Process engineers at the foundry can use it to define rules and verify that their definition is complete and accurate against their test data. DRC deck programmers use the same iDRM description to generate test structures and validate their DRC deck implementation against a correct-by-construction reference. The use of iDRM accelerates the development of the design enablement infrastructure for new process technologies and improves the quality of the physical design kit.
Ease of use is enabling new rule-based use models
iDRM is an enabling technology, enabling non-programmers to quickly capture new rules and define checks clearly and formally without writing any code. As such, it enables and opens up new rule-based use models for a much broader potential user community. For example: (a) for high performance custom designers: creating an additional set of design quality rules on top of the foundry rules and (b) enabling process technology and failure analysis engineers to define yield sensitive shapes and rules, and get complete statistical information on the occurrence , exact dimensions and locations of all such shapes in a physical design. (see figure 2 below)
Fig. 2: histogram of all values of the design rule parameters used in a design
“Over the last 20 years the EDA industry’s efforts in physical verification were all focused on addressing the increasing design capacity & complexity and shortening the final check runtime. With today’s abundance of relatively low cost compute resources, capacity and speed have become commodities. Due to the increasing number and complexity of design rules in 20nm and below, the bottleneck in physical verification has now shifted to the time and effort it takes to create and qualify a DRC deck” said Coby Zelnik, President and CEO of Sage-DA. “iDRM addressed this problem, enabling very quick, yet clear and formal design rule capture which is immediately usable as a correct-by-construction check that can verify the rule definition as well as create a golden reference for third party DRC deck developers. “
Lattice Semiconductor on iDRM
One of iDRM’s early adopter customers is Lattice Semiconductor Corporation. BP Wong, Chief Engineer, R&D at Lattice, said: “iDRM enables us to implement our unique design methodology that results in improved performance, as well as power while minimizing the impact of variability resulting in a design with a predictable yield for a rapid production ramp. The DRC decks from the foundries are designed to maximize the number of wafers that will pass WAT (wafer acceptance test) which is not necessarily the only objective we are seeking.”
Wong continued: “The standard DRC checks from the foundry offer us no competitive advantage when we are on the same process node and using the same standard tools as others. iDRM offers us the ability to maximize the process entitlement in a way that is not possible with any other tools available in the EDA market.”
Wong concluded: “Being an early adopter of iDRM gives us the competitive advantage, enabling us to quickly and graphically capture complex design rules that enable our unique methodology for the best PPA (power, performance, area) for any given node.”
Choon-Hoe Yeoh, Senior Director, EDA tools and Methodologies at Lattice Semiconductor, added: “iDRM rule capture vs. programming a DRC deck can be compared to schematic capture design entry vs. writing a transistor netlist. It provides similar benefits in terms of ease of use, productivity, visual clarity, conciseness and avoidance of errors.”
iDRM is available for sale now, and is already in use by a few early adopter customers. Pricing depends on configuration. Contact firstname.lastname@example.org for more product and sales information.
About Sage Design Automation
Sage-DA provides design rule consistency and closure between manufacturing process limitations, their respective DRM (design rule manual) representation and their DRC deck implementation. Sage-DA’s breakthrough iDRM (integrated design rule management) technology integrates an easy-to-use graphical design rule capture with instantaneous checking capability. iDRM enables non-programmers to quickly capture design rules and generate correct-by-construction checks, accelerates the development and availability of design rule checks for new process technologies and ensures their correctness and consistency, delivering higher yield and faster production ramp up of integrated circuits (ICs) in advanced process nodes.
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