And if you do use more than one, I’ll also bet you have wished the tools from FPGA vendors were more alike. This goes way beyond just the design capture stage, into simulation and debug. With enough experience, you’ve probably found some EDA vendor tools do a complex job like simulation better, and have gotten used to a hand-off from the FPGA vendor design tool and back.
On top of that, I’m guessing you have also had the disappointing experience of wanting to try out a cool new part from another vendor – we have a couple relatively new companies creating some fantastic stuff – but thinking no, that would mean investing in and learning yet another bunch of new tools. So you pass on looking outside your FPGA comfort zone.
That is, until you are forced to. You change jobs, or you are handed a design from somewhere else in your company, or a third party shows up with a design you have to debug. You learn fast, but it takes time and a lot of midnight oil when under pressure to deliver a working product.
It gets even more interesting. Ever had to archive tools with a design, because someone somewhere was afraid the FPGA couldn’t be reproduced? Instead of actually documenting how a design went together, capturing versions of everything used in the tool chain and IP, the thought process is just store the build environment somewhere. Be sure to store the computer it was built on too, BTW, and hope the hard drive starts up ten years from now.
I’m not implying FPGA vendors make bad tools. For some jobs, they may be world class. But, if you are in a situation where more than one FPGA vendor, design language, or design flow is in play, you should be looking at a more integrated FPGA design tool like Aldec Active-HDL.
Active-HDL brings together support for FPGA platforms from multiple vendors with one integrated development environment, able to deal with multiple design entry types, and providing more flexibility in how designs are analyzed and documented. (Daniel Payne has a bit more technical look at Active-HDL in his recent post.)
Project management capability stores everything, from the device hardware configuration to libraries used and synthesis and place & route tools used. This not only has applications for long-term archiving but for the nearer term basics of revision control, especially between teams that may not be using the exact same vendor tools.
There are also code coverage features, something rarely found in vendor tools, which is useful not only in DO-254 situations but also in general cases where third-party IP is involved and teams are less intimate with the internals of the design blocks. Active-HDL also integrates advanced dataflow debugging, which can help trace events across the entire design, and offers up to 6x faster design simulation capability than FPGA vendor tools.
If you find yourself working with one FPGA vendor and their tools environment, you may be fortunate enough to have everything you need there. For that day when your FPGA comfort zone suddenly changes, or you need better management, simulation, or coverage analysis, keep Active-HDL in mind.
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