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  • Solido CEO on 20nm/16nm TSMC and GLOBALFOUNDRIES Design Challenges

    Article: Captain Ahab Calls Out for the Merger of nVidia and AMD-amit-solido.jpgEDA needs more CEOs like Amit Gupta. Solido, which is now profitable, is his second AMS EDA company. The first, Analog Design Automation (ADA), was purchased by Synopsys for a hefty multiplier. Prior to becoming an EDA entrepreneur, Amit was product manager for the wireless group at Nortel and a hardware engineer for the RF communications group at Harris Corporation. I like the Q&A blogs Daniel and Paul do on SemiWiki so here is my first one:

    Q: What are the specific custom IC design challenges your customers are facing?

    We segment the challenges our customers are facing in the following areas:

    1. PVT Corner design. PVT variation encompasses process (FF, SS, FS, SF, TT model corners), voltage, temperature, load and parasitic based variation. When taking all the combinations of these parameters, our customers end up having 1000’s or 10,000’s of corner combinations to simulate. The challenge is that to simulate all the corner combinations is accurate, but very slow. Guessing which corners to simulate is faster, but inaccurate.
    2. 3-sigma Monte Carlo design. The process model corners that foundries like TSMC or GLOBALFOUNDRIES release in their PDK’s are not well suited to individual designs. They are either overly conservative leading to overdesign, or overly optimistic leading to yield loss. As a result, foundries are now releasing local and global statistical variation models for designers to run Monte Carlo analysis simulation on their designs. However, brute force Monte Carlo SPICE simulation is slow, inefficient, and time consuming to use in the design loop.
    3. 6-sigma Monte Carlo design. For designs that are being replicated 1000’s or more times, designing to 6-sigma becomes important. Examples include bit cells for memory design or standard cell library designs. To design to 6-sigma, 5 billion Monte Carlo sample simulations would be needed that would take years and therefore impractical. Alternatively, designers are designing to 3-sigma, and extrapolating to 6-sigma but this methodology is inaccurate. Some companies have developed internal importance sampling techniques, but these don’t scale and suffer from accuracy issues.
    4. Variation debug. If the design is failing PVT corner, 3-sigma or 6-sigma Monte Carlo verification steps, designers need to identify the design sensitivities to variation and figure out how to fix the design, making it robust to variation. Manually changing the device sizes and running PVT or Monte Carlo analysis to check whether the changes fix the design is tedious and time consuming.

    As you can see, the common theme is that the number of SPICE simulations required to get complete design coverage is exploding, which is leading designers to compromise accuracy to get their designs out sooner, or compromise design time to get accurate results.

    Our customers are facing these challenges when doing memory, standard cell, lower power and analog/RF design.

    Q: What does Solido Design do?

    Solido provides variation analysis and design software for custom IC’s so that our customers can achieve maximum yield and performance in their designs. Solido’s product, Variation Designer, boosts SPICE simulator efficiency while increasing design coverage. Solido Variation Designer is being used by top semiconductor companies to design memory, standard cell, analog/RF and low power custom IC designs at leading design nodes including TSMC and GLOBALFOUNDRIES 40nm, 28nm, 20nm, 16nm.

    Q: Why did you start Solido?

    This is the second EDA startup I founded – I really enjoy entrepreneurship and the process of starting and building a business to address user challenges. I co-founded Solido in 2005 after my previous company, Analog Design Automation, was acquired by Synopsys. We talked to many companies about upcoming challenges they were facing, and quickly realized that variation in custom IC design was a common theme. We then raised about $10 million in investment capital and worked very closely with lead companies in developing the v1.0 alpha of our product – Solido Variation Designer. Now, we are releasing Solido Variation Designer v3.0 which is in use by top semiconductor companies and qualified by the top foundries.

    Q: How does Solido help with your customers’ custom IC design challenges?

    Our customers use the following capabilities in our Variation Designer product:

    1. Fast PVT. Our customers use Fast PVT to automatically figure out which are the worst case corners while simulating only a fraction of the corner combinations. This leads to far fewer simulations than brute force PVT corner analysis without compromising accuracy.
    2. Fast Monte Carlo. Our customers use Fast Monte Carlo to cut down the number of simulations to achieve 3-sigma design without compromising accuracy, and extract design specific 3-sigma corners to design to.
    3. High-Sigma Monte Carlo (HSMC). Our customers use High-Sigma Monte Carlo to get the 5 billion Monte Carlo accuracy runs in only a few thousand simulations. This is a dramatic reduction in SPICE simulations and improvement in design coverage. Solido High-Sigma Monte Carlo is fast, accurate, scalable and verifiable.
    4. DesignSense. Our customers use DesignSense to automatically identify design sensitivities to variation, so that users can quickly make necessary design changes and verify that it’s meeting specifications.

    Overall, while SPICE simulator companies are focused on improving speed, accuracy and capacity of their tools, Solido is complementarily focused on intelligently figuring out what to simulate giving better design coverage in a reduced number of simulations than brute force.

    Q: What are the tool flows your customers are using?

    Our customers use Solido Variation Designer with their SPICE simulator of choice. Variation Designer is integrated with Cadence Spectre/SpectreRF/APS, Synopsys HSPICE/HSIM/FineSim/XA, Mentor Eldo, BDA AFS, Agilent GoldenGate. Through our partnership with Cadence, Solido Variation Designer is integrated with Analog Design Environment (ADE), or alternatively our customers input designs through the command line. Variation Designer is integrated with Platform LSF, Oracle Grid Engine and Runtime Design Automation NetworkComputer to run 10’s or 100’s of simulators in parallel. Finally, Solido is qualified in the TSMC, GLOBALFOUNDRIES and STARC reference flows for variation analysis and design.

    Q: What is the roadmap for Solido?

    We’ve developed a rich custom IC design software platform:

    1. Through our vendor partnerships, we have robust integration with design environments, SPICE simulators and cluster distribution tools.
    2. Through our foundry partnerships, we have rich PDK integration to read corner, local and global statistical variation and insight into variation effects at advanced nodes.
    3. By working closely with our customers, we have developed algorithmic engines in support of user tasks that dramatically reduce the number of simulations without compromising accuracy.

    Going forward we will continue to work with customers and foundries to address advanced node custom IC design challenges. Having a custom IC design software platform allows us to build new capabilities very quickly and efficiently by leveraging our existing software integrations and enhancing, adapting and inventing algorithmic engines.

    Q: Will you be at the Design Automation Conference this year?

    Yes, we will be exhibiting at DAC. Readers can sign up here for a Solido Variation Designer demo:

    Q: Where can readers get more information?

    Some sources of more information:

    1. Fast PVT white paper is available for download here:
    2. High-Sigma Monte Carlo white paper is available for download here:
    3. We published a book with Springer called Variation-Aware Custom IC Design: A Hands-on Field Guide. It is available for purchase here:
    4. You can contact Solido directly at

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