WP_Term Object
(
    [term_id] => 1012
    [name] => Concept Engineering
    [slug] => concept-engineering
    [term_group] => 0
    [term_taxonomy_id] => 1012
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 36
    [filter] => raw
    [cat_ID] => 1012
    [category_count] => 36
    [category_description] => 
    [cat_name] => Concept Engineering
    [category_nicename] => concept-engineering
    [category_parent] => 157
)
            
WP_Term Object
(
    [term_id] => 1012
    [name] => Concept Engineering
    [slug] => concept-engineering
    [term_group] => 0
    [term_taxonomy_id] => 1012
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 36
    [filter] => raw
    [cat_ID] => 1012
    [category_count] => 36
    [category_description] => 
    [cat_name] => Concept Engineering
    [category_nicename] => concept-engineering
    [category_parent] => 157
)
Concept Engineering
Posted on by Daniel Payne

Circuit Analysis & Debugging

Circuit Analysis & Debugging
by Daniel Payne on 03-30-2013 at 3:18 pm
Categories: Concept Engineering, EDA

In EDA we often talk about how fast a SPICE circuit simulator is, or about capacity and accuracy compared to silicon measurements. Yes, speed, capacity and accuracy are important, however when talking to actual transistor-level circuit designers you discover something quite different, most of their time is spent doing debugging, looking at waveforms, reading tables of text results, and trying to understand why the circuit is acting differently than intended. In order to really understand what is happening with your newest IP block or re-used IP, you need some automation help in looking at the netlist or interconnect in a visual way.

Fortunately there is help and it comes in the form of an EDA tool that lets you visualize any SPICE netlist so that you can quickly traverse it. Talking about it doesn’t do much justice, so instead I invite you to attend an online webinarhosted by Concept Engineering and EDA Direct, scheduled for Tuesday, April 9th from 10AM to 11AM, PDT.

Webinar
Here’s what will be covered during the webinar:

  • Understand the topology and function of the circuit without having schematics
  • Automatic Schematic generation from Spice, DSPF, LVS Spice, Spectre
  • Traverse hierarchy, search nets/instances very fast
  • Cross probing with GDS for highlighting nets
  • Verify connectivity especially for multi fanin and fanout nets
  • ERC Checking: Floating input and output nets, heavy connected nets, etc.
  • Generate design statistic & reports: Instance & primitive counts
  • Turn on/off Parasitics from extracted netlist to debug designs quickly
  • Debug power/ground connectivity issues
  • Analyze results of LVS runs and use the automatically generated schematics from the extracted SPICE netlists with RC network
  • Full chip netlist tracing (top level integration and block level)

EDA Tools
The German-based engineers from Concept Engineering have a range of tools to help you analyze and debug your IC designs:

  • Transistor-level debugging
  • Gate-level debugging
  • RTL-level debugging
  • Mixed-signal debugging (Transistor, Gate and RTL)

Further Reading

Share this post via:

Comments

0 Replies to “Circuit Analysis & Debugging”

You must register or log in to view/post comments.