Get ready for two full days of content with more than a hundred tracks and keynotes by Lip-Bu Tan, President and Chief Executive Officer, Cadence - Young Sohn, President & Chief Strategy Officer, Samsung Electronics - and Martin Lund Sr. Vice President, Research & Development, SoC Realization Group, Cadence.
What’s Happening at CDNLive Silicon Valley 2013:
March 12-13, 2013
Santa Clara, CA
Papers: Choose from a wide variety of user-authored papers addressing all aspects of design and IP creation, integration, and verification. Discover how others are using Cadence technologies and techniques to realize silicon, SoCs, and systems—efficiently and profitably.
Techtorials: Participate in a variety of interactive techtorials to get a more in-depth look at specific Cadence products, new solutions, and feature enhancements.
Keynote speakers: Hear from industry leaders who influence the global electronics marketplace. They will discuss industry trends in silicon, SoC, and system realization and share their thoughts on the most pressing design challenges.
Designer Expo: Learn more about the collaborative ecosystem available to support you. Cadence and our partners will showcase the latest results of our joint efforts. Explore new products and services from our many exhibitors.
Networking opportunities: Engage in stimulating technology discussions with your peers and stay connected after the conference.
CONNECT. SHARE. INSPIRE.
Not only do Paul and I get in for free, we will be having lunch with Cadence executives (the privileges of blogging on SemiWiki). After lunch we get private briefings. Mine is with Martin Lund, if you have questions you would like asked let me know. Preferably ones that make me look smart!
Here are the tracks I’m most interested in:
MIX101 Data Management for Mixed-Signal Designs, ClioSoft, Inc.
SYS204 How ARM® Software Development Tools can Accelerate Your Time To Market ARM
AVD201 Technology and Design co-optimization for 10nm and Beyond GLOBALFOUNDRIES
AVD202 Designing with 14nm FinFET Technology Cadence
AVD203 14nm FinFET implementation of an ARM Cortex-A7 Samsung/Cadence
AVD204 Designing with Layout Dependent Effects (LDE) in TSMC Advanced CMOS Processes TSMC
SFF206 Scalable Power Sign-off Methodology for Ultra Large Design NVIDIA
AVD207 The DRC + Pattern Database GLOBALFOUNDRIES
CDNLive Silicon Valley brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems. And, you’ll have the chance to talk directly with the Cadence technologists who develop your tools.
CDNLive Silicon Valley 2013 registration includes:
- Attendance at keynote presentations
- Access to Cadence R&D and technology experts
- More than 80 technical sessions, techtorials, and demos
- Access to the Designer Expo
- Access to all networking event
- Lunches and coffee breaks for the duration of the conference
If you have not registered for CDNLive yet you can do so HERE. Try the promo code DCPCDN13 for a reduced rate. See you there!