800x100 static WP 3
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 3886
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 3886
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
)

Oasys at DAC: Right Here, Right Now

Oasys at DAC: Right Here, Right Now
by Paul McLellan on 05-29-2012 at 9:01 pm

 What is Oasys up to this year? For the last three years they have only had videos outside of their demo suite. The first year was a rock video, featuring Joe Costello (chairman off the board) and the executive management. The second year was parodies of the Mac vs PC ads with no prizes for guessing which one Oasys was. And last year was the surfing video filmed down at Santa Cruz. The real capability of RealTime Designer was only on view in the suite.

This year Oasys are letting anyone see the technology. Xilinx and Intel Capital just invested in Oasys. Qualcomm, Texas Instruments and Broadcom (via its Netlogic acquisition) are all users. These are the top US semiconductor companies and they are taping out some of the most difficult designs, right here, right now.

So come by and see a brief presentation about Chip Synthesis. You can even win something. No, not an iPad, something cooler. And there are a couple of demo stations to see the technology in action.

Oasys RealTime Designer reads in the entire design, along with the floorplan. The whole RTL is partitioned, already using coarse placement information in timing and congestion analysis. At all times a fully detailed netlist of each RTL partition is available and is used to accurately time the design. Next, to optimize the design and meet the design constraints, rather than starting to directly operate on these gates (as with traditional synthesis), the original RTL partitions are re-synthesized given their current physical and timing constraints. On top of that, the RTL partitions themselves will get merged, repartitioned and replaced in order to meet timing constraints and reduce any congestion. In a final refine step all gates get a legal placement. This approach, avoiding the step of optimizing a gate-level netlist which makes up most of the run-time of traditional synthesis, generates better results 10-20 times faster.

Oasys are at booth 530. To register for a suite demo go here. To see the presentation or see a demo on the show floor you just need to turn up.

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