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  • AMS Design using Co-Simulation

    The big three vendors in EDA offer AMS simulation tools but what about simulation choices from other EDA vendors?

    It turns out there are two privately held EDA companies that have done business since the 1980's and have just integrated a Verilog A simulator with a SPICE circuit simulator. The two companies are Aldec with a Verilog A simulator and Tanner EDA with a SPICE circuit simulator. To learn more about this AMS simulation capability I reviewed a webinar from March 8th, 2012.

    Article: Who Needs a 3D Field Solver for IC Design?-aldec_crescent_rgb_sm.jpg

    Jeff Miller presented for Tanner EDA and Jerry Kaczynski for Aldec. Each company has over 30,000 EDA licenses in use worldwide.

    The AMS tool flow starts with design capture in S-Edit then an automated netlist out to T-Spice AMS which uses Verilog A in Aldec's Riveria PRO and SPICE in Tanner's T-Spice:

    Article: Who Needs a 3D Field Solver for IC Design?-tool-flow.jpg

    Waveforms for analog signals are viewed in the Tanner viewer, while digital signals are viewed in the Aldec tool:

    Article: Who Needs a 3D Field Solver for IC Design?-viewer.jpg

    With Riviera-PRO the digital simulator features:
    • Verilog, VHDL, SystemVerilog, SystemC
    • Assertion-based verification
    • Command line or GUI operation
    • Code and functional coverage
    • Transaction-level debugging
    • APIs to communicate
    • Runs on Linux, Windows XP, Vista and Windows 7

    This is a co-simulation approach, not a single kernel approach like that offered by Synopsys, Cadence and Mentor. For most AMS netlists the SPICE simulation will usually limit the run time.

    The demo showed an ADC design where capture is done in Tanner's S-Edit tool then netlisted. S-Edit automatically detects what block is netlisted for Spice and for Digital. T-Spice is run on the netlist which then invokes the digital simulator, Riviera-PRO.

    Article: Who Needs a 3D Field Solver for IC Design?-adc-design.jpg

    Q: Does the logic netlist run through the T-Spice input file buffer, causing capacity issues?
    A: There isn't a character limit to T-Spice parsing, so we don't know of any capacity issues.

    Q: Is it better to use a 64 or 32 bit OS for my AMS simulation?
    A: It really depends on your memory requirements. For large memory requirements then you could run out of memory space on a 32 bit OS, so then use the 64 bit version on Linux or Windows for Riveria. On the SPICE side you can also use either 32 or 64 bit versions.

    Q: Which OS versions are supported for this AMS co-simulation?
    A: Windows 32 bit or 64 bit, Linux only 32 bit on the SPICE side.

    Q: If I have a mixed signal design can I independently specify a Verilog and SPICE view without using two instance names?
    A: Yes, you can specify per instance if this cell is Verilog or SPICE view.

    Q: Does this co-simulation work with Active-HDL?
    A: Use Riviera PRO for this AMS co-simulation for now. Active-HDL could be added in the future if there's enough demand, it's not a technical issue just a demand issue.

    If you already own a Tanner EDA or Aldec simulator and want to start doing AMS simulation for IC designs then this affordable co-simulation approach should be considered. I'd expect to see in the product roadmap a few useful features like:
    • Unified waveform viewer, instead of two viewers
    • Cross-probing between schematic, source and wave form viewer
    • Interactive simulation where you can start, stop, measure and continue

    The webinar is online here.