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Tag: 20nm

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  1. How To Design a TSMC 20nm Chip with Cadence Tools

    Published by Paul McLellan, 2 Weeks Ago 06:10 PM Tags: cadence  eda  tsmc  semiconductor  webinar  20nm  double patterning  local interconnect 
    • Comments: 0

    CMS:
    Cadence Design Systems

  2. Challenges of 20nm IC Design

    Published by daniel_payne, 3 Weeks Ago 09:38 AM Categories: EDA  Synopsys  Tags: eda  semiconductors  20nm  saleem haider  synopsys 
    • Comments: 8
    Last Post: 1 Week Ago 06:26 AM
    by MicheleR 

    CMS:
    Synopsys

  3. TSMC ♥ Solido

    Published by Daniel Nenni, 3 Weeks Ago 06:00 AM Tags: eda  tsmc  28nm  process variation  semiconductors  20nm  solido  16nm 
    • Comments: 1
    Last Post: 3 Weeks Ago 07:16 AM
    by LinkedIn 

    CMS:
    Solido Design Automation

  4. Moore, or More Than Moore?

    Published by Paul McLellan, 4 Weeks Ago 10:05 AM Tags: foundry  fabless  28nm  semiconductor  gsa  20nm  sip  14nm  interposer  tsv  2.5d  3dic  10nm  silicon summit  gsasummit 
    • Comments: 0

    CMS:
    Global Semiconductor Alliance

  5. TSMC Responds to Samsung!

    Published by Daniel Nenni, 04-12-2013 08:00 PM Tags: eda  tsmc  samsung  semiconductor  finfets  20nm  16nm 
    • Comments: 11
    Last Post: 4 Weeks Ago 12:05 PM
    by Boris 

    CMS:
    TSMC

  6. TSMC on Collaboration: JIT Ecosystem Development

    Published by Paul McLellan, 03-27-2013 12:02 PM Tags: eda  tsmc  synopsys  28nm  finfet  semiconductor ip  semiconductor  20nm  snug  14nm  double patterning  cliff hou  10nm  snug2013  spacer 
    • Comments: 4
    Last Post: 03-28-2013 10:54 PM
    by CharlieD 

    CMS:
    TSMC

  7. Reliability is the New Power

    Published by Paul McLellan, 03-09-2013 07:56 AM Tags: eda  reliability  semiconductor  20nm  date  riif  selse  single event effect 
    • Comments: 1
    Last Post: 03-17-2013 10:06 AM
    by LinkedIn 

    CMS:
    IROC Technologies

  8. Synopsys ♥ FinFETs

    Published by Daniel Nenni, 03-03-2013 04:00 PM Tags: synopsys  finfet  20nm  14nm  raymond leung 
    • Comments: 1
    Last Post: 03-05-2013 04:32 PM
    by John Swan 

    CMS:
    Synopsys

  9. When the lines on the roadmap get closer together

    Published by Don Dingee, 02-28-2013 10:53 AM Categories: EDA  Cadence  Tags: cadence  20nm  modeling  double patterning  optimization  mixed signal  layout-dependent effects  concurrent ppa 
    • Comments: 3
    Last Post: 03-06-2013 10:16 AM
    by leohuf 

    CMS:
    Cadence Design Systems

  10. Magic? No! It’s Computational Lithography

    Published by Beth Martin, 02-11-2013 05:00 AM Tags: mentor  ret  opc  computational lithography  20nm  spie  sraf  ilt  inverse lithography  hotspots 
    • Comments: 1
    Last Post: 02-13-2013 02:57 AM
    by karbapi 

    CMS:
    Mentor Graphics

  11. No EUV before 7nm?

    Published by Paul McLellan, 02-07-2013 11:31 AM Tags: eda  ibm  euv  mask  semiconductor  20nm  14nm  450mm  defect  cptf  7nm  10nm  450mm wafers  pellicle 
    • Comments: 18
    Last Post: 11 Hours Ago 04:14 AM
    by Staf_Verhaegen 

    CMS:
    Events

  12. Double Patterning for IC Design, Extraction and Signoff

    Published by daniel_payne, 01-21-2013 01:27 PM Categories: EDA  Synopsys  Tags: eda  tsmc  synopsys  semiconductor design  20nm  double patterning  cowos  anderson ghiu 
    • Comments: 15
    Last Post: 01-27-2013 11:49 AM
    by simguru 

    CMS:
    Synopsys

  13. Common Platform Technology Forum February 5th 2013 Live or Online!

    Published by Daniel Nenni, 02-03-2013 06:00 AM Tags: cadence  synopsys  mentor  arm  globalfoundries  common platform  ibm  samsung  finfet  20nm  14nm 
    • Comments: 4
    Last Post: 01-22-2013 02:24 AM
    by cederstroem 

    CMS:
    The Front Page

  14. Cortex-A9 speed limits and PPA optimization

    Published by Don Dingee, 12-19-2012 01:01 PM Categories: EDA  Cadence  TSMC_Foundry  Atrenta  ARM  Tags: cadence  tsmc  arm  atrenta  28nm  power  20nm  optimization  performance  area  clock speed  process 
    • Comments: 0

    CMS:
    Cadence Design Systems

  15. Double Patterning Verification

    Published by Paul McLellan, 12-10-2012 01:03 AM Tags: eda  synopsys  semiconductor  20nm  double patterning  coloring  verifcation 
    • Comments: 3
    Last Post: 12-15-2012 04:37 PM
    by Paul McLellan 

    CMS:
    Synopsys

  16. How Apple Plans to Leverage Intel's Foundry

    Published by Ed McKernan, 12-09-2012 02:00 PM Tags: 20nm  tsmc  arm  intel  apple  22nm  14nm  x86  qualcomm  processors 
    • Comments: 11
    Last Post: 12-27-2012 03:20 PM
    by Netteligent 

    CMS:
    Intel

  17. Solido and TSMC for 6-Sigma Memory Design

    Published by Daniel Nenni, 11-06-2012 06:30 PM Tags: eda  28nm  semiconductor  20nm  solido  solido design automation  6 sigma  tscm  processvariation 
    • Comments: 0

    CMS:
    Solido Design Automation

  18. Laker3 in TSMC 20nm Reference Flow

    Published by Paul McLellan, 10-16-2012 06:10 PM Tags: eda  tsmc  synopsys  semiconductor  springsoft  20nm 
    • Comments: 0

    CMS:
    SpringSoft

  19. GlobalFoundries Announces 14nm Process

    Published by Paul McLellan, 09-20-2012 06:00 AM Tags: tsmc  globalfoundries  intel  finfet  20nm  14nm  global foundries 
    • Comments: 1
    Last Post: 09-26-2012 01:58 AM
    by anysilicon 

    CMS:
    GlobalFoundries

  20. Cadence at 20nm

    Published by Paul McLellan, 08-21-2012 06:10 PM Tags: cadence  eda  28nm  semiconductor  20nm  variation  double patterning  layout dependent effects 
    • Comments: 0

    CMS:
    Cadence Design Systems

  21. Morris Chang Comments on Q2 2012: 28nm, 20nm, 16nm, FinFets, CAPEX, etc…

    Published by Daniel Nenni, 07-19-2012 03:42 PM Tags: morris chang  28nm yield  finfets  20nm  tsmc q2 2012  2012 capex 
    • Comments: 0

    CMS:
    TSMC

  22. EUV Masks

    Published by Paul McLellan, 07-17-2012 09:00 PM Tags: lithography  euv  mask  semiconductor  20nm  litho  reticle  defect 
    • Comments: 1
    Last Post: 07-18-2012 04:49 PM
    by Paul McLellan 

    CMS:
    The Front Page

  23. How has 20nm Changed the Semiconductor Ecosystem?

    Published by Daniel Nenni, 07-15-2012 05:30 PM Tags: cadence  tsmc  28nm  samsung  intel  umc  20nm  fabless business model 
    • Comments: 5
    Last Post: 07-16-2012 04:09 PM
    by CharlieD 

    CMS:
    TSMC

  24. The Scariest Graph I've Seen Recently

    Published by Paul McLellan, 07-01-2012 02:00 PM Tags: eda  28nm  moore's law  semiconductor  22nm  20nm  14nm 
    • Comments: 15
    Last Post: 07-27-2012 03:18 PM
    by loveanalog 

    CMS:
    The Front Page

  25. Understanding and Designing For Variation in GLOBALFOUNDRIES 28nm at DAC 2012

    Published by Daniel Nenni, 06-03-2012 06:30 PM Tags: eda  globalfoundries  28nm  process variation  semiconductor  20nm  solido 
    • Comments: 0

    CMS:
    GlobalFoundries

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