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Variation in custom semiconductor designs causes yield loss and re-spins, which in turn cause delays in delivering products to market and financial losses. To counter the effects of variation, foundries release models that describe variation for each manufacturing process. This model information is then used by designers to estimate the effects of variation during the design cycle, and to improve the design to make it robust to manufacturing variation effects. This is variation-aware custom IC design.

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Cases:

[top]Sense Amp 28nm 25 devices

Using the HSMC+ package
  • Ported from 40nm to 28nm
  • Swept l and w combinations against all worst-case corners in one task
  • Compared all sweep results in one GUI window
  • Verified to 4.948 sigma in 49 minutes

[top]Mux 40nm 54 Devices

Custom digital cell
  • Identified that the falling delay is much larger than the rising delay and the leakage current is too large
  • Discovered key devices to trade off between rising delay and falling delay
  • Improved performance: improved falling delay by more than 80% while only sacrificing 10% of rising delay, improved the leakage by more than 30%
  • Reduced power by 10%

[top]Comparator 45nm 60 Devices

Analog comparator used in ADC
  • Improved performance: fixed comparatorís low phase margin, without sacrificing other important specifications
  • Improved productivity: completed this task in 3 hours that took 1 month to do manually

[top]Receiver ADC 65nm 10,000 Devices

ADC used in a transceiver
  • Identified approximately 10 sensitive devices that needed to be adjusted
  • Post-layout design (with over 10,000 devices) was also verified
  • Improved parametric yield from 40% to 100%

[top]Voltage Regulator 65nm IDM 600 Devices

IP block in a power management IC for mobile applications
  • Verified that the design meets specifications across statistical variations
  • Identified that the margin on the output characteristic was insufficient
  • Improved parametric yield: increased design margin by 2.5x
  • Improved productivity: reduced design time by 1 week

[top]Bandgap Reference 65nm 350 Devices

IP block in a power management IC for mobile applications
  • Identified a parametric yield problem due to startup time (yield = 16%)
  • Identified a key weakness in the startup circuit that was causing the problem
  • Improved performance: fixed the weakness in the startup circuit by changing its topology
  • Improved parametric yield from 16% to 100%

[top]LDO Voltage Regulator 65nm 300 Devices

IP block in a power management IC for mobile applications
  • Identified a risk of design failure due to oscillation at high temperatures
  • Identified the devices that impact the oscillation robustness
  • Improved performance: eliminated the oscillation problem in one testbench by resizing two high-impact devices
  • Improved performance: protected design against oscillation by increasing external capacitance specification to avoid circuit failure

[top]Charge Pump 65nm 200 Devices

Charge pump used in a PLL
  • Identified that the offset is too large
  • Discovered that a key differential pair had a high impact on the offset variation
  • Improved performance: resized the key differential pair and the overall offset distribution was reduced by approximately 40mV

[top]Sigma-Delta ADC Opamp 65nm 100 Devices

Part of a radio front-end
  • A power supply rejection ratio (PSRR) problem existed
  • Improved productivity: manual analysis without Variation Designer took 2 weeks compared to 3 hours with Variation Designer

[top]SAR Comparator / Pre-amp 65nm 94 Devices

Comparator / pre-amp in a successive approximation ADC
  • Identified an offset problem causing parametric failure
  • Identified the key devices that were causing the offset problem
  • Improved parametric yield: fixed the design, eliminating the offset problem by changing the sizing ratio of the key devices
  • Improved performance: decreased load capacitance without introducing additional offset
  • Improved productivity: avoided tape-out delay

[top]High-speed Display Driver 65nm 80 Devices

Display driver
  • Identified proximity effects that could cause possible circuit failure with pre-layout schematic
  • Discovered 8 devices were particularly sensitive to proximity effects
  • Modified the layout of the sensitive devices and eliminated the sensitivity to well proximity effects
  • Improved productivity: fixed the design in 1.5 days with Variation Designer instead of using 2 weeks of designer and layout engineer time
  • Improved parametric yield: avoided a mask re-spin

[top]VCO 65nm 57 Devices

VCO in a PLL
  • Identified that the output frequency is not stable
  • Pin pointed one device that will improve the output frequency
  • Improved performance: resized the device and improved the output frequency by 10%, improved the phase noise

[top]Reference Generator Amplifier 65nm 55 Devices

Analog amplifier
  • Analysis discovered a 5% error variance in the amplifier
  • Without Variation Designer, script-based analysis had incorrectly calculated a variance of only 1%
  • Improved parametric yield: design was fixed to bring the error variance into specification. If the design had shipped without using Variation Designer, a re-spin would have been required

[top]Opamp 65nm 50 Devices

Opamp used in a 10-bit ADC
  • Identified that the design is highly sensitive to mismatch
  • Discovered that phase margin is causing low yield
  • Found highly impacting devices
  • Improved performance: resized the devices and increased the phase margin by about 18% while maintaining sufficient margin for DC gain

[top]Flip Flop 65nm 34 Devices

Custom digital cell
  • Idenitified that the setup time and hold time are not satisfy requirements (yield = 20%)
  • Discovered the most impacting devices on setup time and hold time
  • Improved performance: resized the key devices and improved both the setup time and hold time by about 30%

[top]1-of-N Domino Logic Cell 65nm 27 Devices

Custom digital cell
  • Identified that the power consumption and delay are not satisfying requirements (yield = 30%)
  • Discovered the most sensitive devices to delay and power
  • Reduced power: resized the key devices to improve the power by 30%
  • Improved performance: resized key devices to improve delay by 10%
  • Improved parametric yield to 100%

[top]Pipelined ADC 90nm 3,000 Devices

Eight-stage pipelined ADC
  • Identified a signal-to-noise ratio (SNR) problem in the design
  • Improved designer productivity: analyzed design 50x faster than with Monte Carlo
  • Improved performance: fixed the SNR problem by resizing the design

[top]GMC filter 90nm 190 Devices

Analog filter used in a transceiver
  • Identified circuit failure due to attenuation and bandwidth not meeting requirements (yield = 0%)
  • Discovered key devices impacting the yield
  • Improved parametric yield to 100% by resizing the key devices
  • Reduced area by over 10%
  • Reduced power by over 10%

[top]Mixer 90nm 162 Devices

Analog mixer used in a transceiver
  • Identified low temperature caused high power consumption
  • Discovered the trade off between output current and power
  • Pin pointed 2 devices which highly impacted output offset
  • Improved performance: resized the key devices to reduce output offset by more than 50%
  • Reduced power: resized the devices to trade off some current output and improved the power by 15%

[top]Cascode OTA 90nm 160 Devices

OTA used in a pipelined ADC
  • Identified that noise is too large and caused circuit failure (yield = 10%)
  • Identified the most impacting devices on noise
  • Improved performance: resized the impacting devices and improved the noise by 40%
  • Reduced power consumption by 20%

[top]Telescopic Opamp 90nm IDM 27 Devices

Opamp used in an ADC
  • Identified a yield problem caused by DC gain (yield = 69%)
  • Discovered an unexpected correlation between DC gain and phase margin that could be exploited to improve yield
  • Identified key devices impacting the tradeoff between DC gain and phase margin
  • Improved parametric yield to 93% by resizing the design to trade off phase margin for DC gain
  • Improved designer productivity: saved several days of manual effort

[top]Shift Register 130nm 230 Devices

Custom digital cell
  • Identified falling delay causing circuit failure (yield = 30%)
  • Discovered the most sensitive devices that impacted delay
  • Improved parametric yield: resized the key devices to improve the yield to 100%

[top]NBTI detect circuitry 130nm 20 Devices

Build-in NBTI detect
  • Identified the reference voltage is very unstable under environmental and statistical variation.
  • Redesigned the voltage reference and made Vref vary less than 1% with environmental and statistical variation
  • Improved parametric yield from 5% to 100%

[top]Sense Amplifier 130nm 9 Devices

SRAM sense amplifier ported from 180-nm technology
  • Identified a parametric yield problem (yield = 30%)
  • Improved parametric yield from 30% to 99.9% by resizing the design
  • Improved designer productivity: analyzed design 130x faster than with Monte Carlo


Reference: Solido Design Automation

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