If the IP market is a niche market (see:
IP paradox blog) with revenue of about $3 billion, or 1% of the overall semiconductor business, how could we qualify the Verification IP (VIP) market…is it a “super-niche” market? In fact, the verification of the IP integrated into a SoC is an essential piece of the engineering puzzle when you are involved in SoC design. We will address the verification of any protocol based function, which can be an Interface protocol (USB, PCIe, SATA, MIPI and more), a specific memory Interface (DDR, DDR2,…, GDDR,…, Flash ONFI and more) or a Bus protocol (AMBA AXI,…, OCP and more).
The principle of this type of VIP is: you write Test benches, send to a scenario Generator which activates the Drivers of the Bus Function Model (BFM), accessing the function you want to verify, the Device Under Test (DUT). The Verification Engine itself is made of the transaction Generator, Error injector and so on; and of the BFM, which is specific to the protocol and to the agent configuration: if the DUT is a PCIe Root Port x4, the BFM will be a PCIe End Point x4. If the DUT is the hand, the BFM is the glove. When you write Test benches, you in fact access to a library of protocol specific test suite (test vectors written by the VIP vendor), which is sold on top of the VIP. So, after applying test benches, you can monitor the behavior of the DUT and check for the compliance with the protocol specification. This defines another product sold by the VIP vendor: the Monitor/Checker, which allows you to evaluate both the coverage of your Test Benches, and the compliance in respect with the protocol.
It is important to notice that the same word (VIP) can be used to qualify two very different design tasks. When you design from scratch a protocol based function (say a USB 3.0 Controller), whether it will be to use it within your own SoC or to market it later as an IP product, you will have to run extensive, computer time consuming, and hopefully very exhaustive Verification “campaign”. You will need to use computer farm concept, and acquire the equivalent number of “seat licenses”, ending up to a cost in the same range than the equivalent IP license price. It makes sense if you plan to reuse this function across various SoC. Now, when you integrate the same function (acquired IP of internally developed), you will need to verify the behavior of this IP being integrated into the complete design in respect with the protocol, but you probably don’t need to run again the overall verification campaign, assuming it has been done previously. In this case, you will run a subset of the verification, the cost associated with VIP should be much lower. In both cases we call it VIP, but there is probably one order of magnitude between the cost, and even more if you consider the computer run-time.
Common sense remark about the BFM and IP: when you select a VIP provider to verify an external IP, it is better to make sure that the design team for the BFM and for the IP are different and independent (high level specification and architecture also made by two different person). This is to avoid the “common mode failure”, principle well known in aeronautic for example.
Now, if we try to evaluate the market size of the VIP, like we can do for the Design IP, we realize that there is no market data available. We simply don’t know the size of this market! Is VIP an attractive market for the top 3 EDA vendors, like IP is? During the 2000’s, the VIP market was very crowdie with small to medium size companies, with a typical profile: Engineering based in Asia (India) and sales, marketing and head quarters in the USA. As we will see with the VIP vendor list, Cadence has started an acquisition campaign in 2008, ending with Denali acquisition in 2010, and Synopsys is doing the same in 2011-2012. VIP market is consolidating; we can guess that it is seen as strategic enough for the big guys from EDA, as they are still investing in it!
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[hide][top]Verification IP vendors
Avery is supporting PCIe and USB 2.0 and SATA VIP for several years; they now support USB 3.0 VIP (Verilog and SystemVerilog OVM/VMM).
List of VIP from Avery:
- PCI Express 1.1, 2.1, and 3.0
- USB 2.0/OTG, 3.0, xHCI, and UAS
- SATA 1,2,3
- AMBA AHB and AXI3/4
Avery does not propose design IP, neither design services.
Their verification tool, Incisive ABA VIP uses assertion-based verification (ABV) techniques. Incisive VIP is compliant with the Open Verification Methodology (OVM), and supports multiple languages including SystemVerilog, e, Verilog®, and VHDL. Cadence offer different VIP strategies: signal-based or Transaction based acceleration, for the later with UVM or C user interface that the designer will select depending on their specific needs (see picture).
Cadence provide, on a per protocol basis, test bench VIP, assertion-based VIP, transaction-based acceleration VIP. Back in October 2008, they have made several acquisitions of VIP products from HDL Design House, Yogitech SpA, IntelliProp Inc. Now, the existing portfolio of Cadence UVCs supports:
Cadence has even more heavily invested into this market with Denali acquisition in 2010 (for $315M), they bought a strong IP and VIP port folio and competencies, and probably good market share. This includes the Memory models, PCIe and USB VIP and DDRn functional IP. If we had to qualify Cadence’ positioning, we would say that they focus on the high value VIP, which means they try to quickly provide a solution for the verification of the emerging protocols:
Company acquired by Synopsys in February 2012
Company acquired by Synopsys in November 2011
PerfectVIP deliver a SystemVerilog-based OVM compliant VIP. Their Verification IP products include:
Interfaces VIP
- USB 3.0
- USB 2.0
- PCIe Gen-3, Gen-2, Gen-1
- ONFI
- Ethernet
- SPI 4.2
Storage VIP
Buses VIP
- AMBA AHB
- AMBA APB
- AMBA AXI
- SMBus
PerfectVIP offers full-service support for SOC and ASIC designs, from customer’s specification to GDSII with full verification in ASIC, FPGA, board design and Software and Firmware development.
Sibridge's offers native SystemVerilog Verification IPs with support for OVM/VMM/UVM methodologies. Sibridge Verification IP solutions are customer proven, high performance, rich featured with usability flexibility, superior user interface, and customizable VIP components with comprehensive documentation. The VIPs are easily configurable and allow multiple instances creation.
The Verification IP portfolio consists of
- PCI Express Gen1, Gen 2, Gen3
- Ethernet 10M/100M, 1G, 10G, 40G, 100G
- USB 2.0, USB 3.0
- AMBA – AHB/APB
- AMBA - AXI
- SATA I,II
- MIPI
- I2C
- UART
- SPI
The company offer BFM based VIP in the following segments:
- MIPI CSI-2, SPMI, HIS, DSI, RFFE
- ONFI, NFC, eMMC, SDIO 1.0/2.0/3.0, Fibre Channel
- Interlaken, SPI, Ethernet (MAC, 10/100/1000, XAUI, KX, KX4, KR,40/100, KR4, CR10)
- I2C, SMBus, I2S, Opencore Wishbone B3, OCP, AMBA 4 AXI
- USB 3.0, USB 2.0, DDR3, DDR2, RapidIO
At the beginning of 2011, it was possible to say that Synopsys was focusing on design IP, and only offering BFM type of VIP (when Cadence was focusing on VIP, that was the “Yalta” concept, meaning that the two EDA giants were sharing the IP & VIP market like USSR and USA has shared the world in 1945). Then came two acquisitions (nSys and ExpertIO), and the Discovery product launch in February 2012. This move clearly demonstrates the new Synopsys’ strategy, based on a product 100% SystemVerilog based and supporting natively UVM, VMM and OVM.
The offer from Synopsys in verification is straightforward, as we can see on this architecture description:
This also means that the customer will not have the choice to optimize for simulation run time or for protocol compliance, this tend to indicates that Synopsys wants to target the mainstream market, proposing one solution only, to mimic their strategy in the interface IP market, where addressing the mainstream has been the way to success. The port-folio is covering most of the interface protocols, but is not as exhaustive as far as the memories are concerned:
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