FD-SOI Wiki

FD-SOI stands for fully-depleted silicon-on-insulator. The term FD-SOI typically refers to a planar transistor architecture. Planar architectures are pretty much what the industry's been doing for decades, but with FD-SOI, it's done on an SOI wafer with very thin top silicon over a very thin layer of insulating Buried Oxide (aka BOX). This confers significant advantages in terms of power, performance and area at an extremely competitive final cost.

The current thinking is that FD-SOI will bridge the gap starting at the 28nm node and running through around the 14nm node (maybe beyond), when FinFETs are ready. (FinFETs are fully-depleted transistors, too, but they have a vertical orientation, hence the “3D” or “vertical” moniker. They can be built on bulk or SOI wafers, too, but that's for another wiki.)

Contents
The Basics
Brief History
Design Perspectives
Foundries / Wafers
Resources

The Basics





(The illustrations above were taken from A Primer on FD-SOI by the SOI Industry Consortium.)


Brief History

Although a somewhat different technology from the newest generations, Oki Semiconductor (now known as Lapis Semiconductor) has been shipping commercial, FD-SOI LSIs since 2002 (see OKI: The Industry’s Commercial FD-SOI Pioneer). It's at the heart of many of Casio's highly-successful G-Shock watches. However, the Oki/Lapis architecture does not require the ultra-thin SOI wafers of the latest technology.

But the latest FD-SOI technology for scaling advanced CMOS nodes is based on a transistor with an ultra-thin body (UTB). Former TSMC CTO and Berkeley professor Chenming Hu and his team published seminal papers on FinFETs (1999) and UTB-SOI (2000). As he noted in a recent article, “Planar FD-SOI requires SOI wafers with a very, very thin top layer of silicon. When we first invented the concept in 2000, the availability of such SOI substrates was the major obstacle. The final silicon layer thickness had to be about a quarter to a third of the gate length. However, Soitec has surmounted the wafer challenge and with that, commercial production can now become a reality.”

Some of the companies and institutions that have historically been most active in the latest developments in the FD-SOI arena (although they sometimes call it by a different acroynm) include STMicroelectronics (ultra-thin body & box / UTB²) Hitachi (hybrid silicon on thin box - SOTB), IBM (extremely thin / ET-SOI), ARM, GlobalFoundries, Soitec (FD-2D), Leti and UCBerkeley. Most belong to the SOI Industry Consortium.

In spring of 2012, it was announced that the first FD-SOI chips would be ST-Ericsson's NovaThor at 28nm in 2012, using STMicroelectronics' technology. In June 2012, STM announced initial manufacturing in-house at Crolles, to be followed by volume manufacturing in 2013 at GlobalFoundries for 28nm. 20nm starts in 2014. An important part of the announcement was that other GlobalFoundries customers would have access to the proprietary STMicroelectronics FD-SOI technology.


Design Perspectives

One of the big advantages of FD-SOI is that from a design point of view, the experts say it's not any harder than a typical half-node port. Here are some good white papers and articles to get started with.

• White paper: Questions and answers on FD SOI technology
  This document is a high level introduction to FD-SOI technology and its applicability to next technology nodes, in the form of a few key questions and their quick answers. No deep technical details are provided here, however Question 15 provides some relevant links. Short answers are provided first (hypertext links are provided, just click on the question of interest), followed by slightly more detailed answers for the interested readers.
  [By Xavier CAUCHY, Digital Applications Manager, Soitec, with François ANDRIEU, Senior Research Engineer, LETI]
  

• White paper: Considerations for Bulk CMOS to FD-SOI Design Porting
  The scope of this study is to examine the efforts required for a straight “port” of an existing bulk CMOS design to FD-SOI at the same node. The objective would be to get value from FD-SOI for a modest redesign effort – even if this means not necessarily taking maximum advantage of the potentialities of FD-SOI. The focus is on FD-SOI with Ultra-Thin Buried Oxide. This document intends to be sufficiently generic to be applicable to different possible implementations of the FD-SOI technology by foundries.
  [SOI Industry Consortium]
  

• White paper: Planar fully depleted silicon technology to design competitive SOC at 28nm and beyond
  STMicroelectronics and GlobalFoundries recently announced that ST's FD-SOI technology would be available to other GF customers. This document by ST gives an excellent overview of their technology. After outlining some implementation choices, a number of circuit-level benchmark results as well as some important design aspects are presented.
  [STMicroelectronics]
  

• ARM's SOI guru Jean Luc Pelloie posted an article last year on the tools they've used in their ports – see Bulk logic designs for mobile apps port directly to FD-SOI. Here's a summary of the EDA tools:
  

• ST-Ericsson's going to be the first to put smart phone chips on FD-SOI. See ST-Ericsson's Technology Blog (April & May 2012) for benchmarks and design considerations:
  

• FD-SOI: A process booster for ST-Ericsson’s next generation NovaThor, Part 1
  
• FD-SOI: A process booster for ST-Ericsson’s next generation NovaThor – Part 2 (Part 2 features an extremely interesting and easy-to-understand speed vs leakage and speed vs dynamic power comparison.)
  

Foundries / Wafers

The first FD-SOI foundry service will be offered by GlobalFoundries using STMicroelectronics' proprietary technology:

• The 28nm FD-SOI generation is scheduled to be available for prototyping by July 2012.
  

• The next node, the 20nm FD-SOI generation, is currently (2012) under development and is scheduled to be ready for prototyping by Q3 2013.
  
• The 28nm FD-SOI Process Design Kit (PDK) is available now (June 2012), targeting risk production by mid-2012. Evaluation SPICE models are now (June 2012) available for the 20nm node, and full PDK is scheduled by end of 2012, with risk production for 13Q3.
  

Wafers for FD-SOI are currently available from a number of sources, including:

• Soitec – Soitec is the world leader in SOI wafer manufacturing. The company leverages its proprietary Smart CutTM manufacturing technology. Uniformity of the top silicon layer of Soitec “FD-2D” wafers is guaranteed to within +/-5Å at all points on all wafers. This uniformity is equivalent to 5 mm over 3,000 km, which corresponds to approximately 0.2 inches over the distance between Chicago and San Francisco.
  
• SEH – SEH (Shin-Etsu Handotai), a subsidiary of Shin-Etsu Chemical, Co., Ltd. is the biggest silicon wafer production company in the world. It has been supplying SOI wafers since 1988. Press reports indicate that the company, which has licensed Soitec's Smart Cut^TM technology for thin SOI wafers since 1997, will also supply FD-SOI wafers.
  

Resources

The biggest repositories of resources about FD-SOI include:

• the SOI Industry Consortium's FD-SOI page
  
• the FD-SOI tag at the Advanced Substrate News website
  
• and now of course, this semiwiki!