Invarian’s goal is to provide the industry’s best solutions for full-chip sign-off analysis for complex, high-performance integrated circuits (ICs). . Today’s chips are too large and complex for existing tools. Achieving accurate results demands a new paradigm. Success requires attacking the problem from multiple angles. Invarian solutions deal with design complexity in a variety of ways. By shifting the methodology to true time domain we solve the problem of scale. Along with the ability to handle large chips comes shorter simulation runtimes without the sacrifice of accuracy. Invarian tools use algorithms designed for today’s parallel computing systems. We are able to leverage the entire compute environment. Our concurrent analysis delivers efficiency and accuracy that existing tools lack. An easy to use backend flow eliminates cumbersome design modifications. The incredibly smaller process geometries in the advanced silicon process technologies are today so expensive that there can be no risk of design failures and often too much guard-band is added which hinders the competitive edge of truly taking advantage of the processes enablement. Whether designs are massive in size with billions of transistors on a single chip or having complex physical features including true 3D stacking that traditional sign-off analysis tools simply cannot handle. By using Invarian’s solutions, designers have the ability to design with accuracy and have the confidence the taped-out design will yield as expected.
Invarian’s Power Platform delivers all the sign-off analysis solutions needed from IR-drop analysis to thermal analysis and power analysis in a concurrent environment that enables fixes as your go, this ability gives designers the confidence to get the most power and performance capabilities with the fastest sign-off time.
Invarian was formed in 2008 and is headquartered in Sunnyvale, California. We have top tier-one customers validating that our technology correlates with physical measurements in silicon in 40nm, 28nm and designs in 20nm and below including true 3D analysis.
Jens C. Andersen
Chief Executive Officer
Jens brings over 18 years of sales acumen in the EDA market with in-depth experience at driving sales at a variety of startups and was an early advisor to Invarian before stepping in as CEO. He played a significant role in influencing product development and the early adoption with leading top-tier customers. Prior to Invarian, Jens held various executive management and sales positions at Cadabra DA, Nangate, Numerical Technologies, Zenasis Technologies and Synopsys. Jens managed US Operations and Worldwide sales at Nangate and was instrumental in achieving sales goals that put Nangate in the top 10 EDA startups revenue position.
VP of Engineering and COO
Alex co-founded Invarian and has over 18 years of EDA experience, with emphasis on IC physical design, customer support, and participation in development of various physical design tools. During his career, he has held various applications engineering positions for several top companies in EDA industry. Prior to Invarian, Alex was in Field Applications management at Nangate, working primarily on development of design optimization flow on the basis of re-synthesis and intelligent library augmentation. He has also served as Principal Applications Engineer for Golden Gate Technology, working on physical design tool (placement, CTS, routing, timing closure). Prior to that, Alex was working for Synopsys as Senior Applications Engineer, focusing primarily on routing/back-end flow and low power design. He received his Master's of Science Degree at Moscow Institute of Electronic Engineering, Moscow, Russia in 1991.
Chief Technology Officer
Vladimir co-founded Invarian and has over 14 years experience in the EDA industry, focusing primarily on developing of IC&PCB physical synthesis and analysis tools. During his career, he served with several top companies in the EDA industry as a software developer, technical leader and R&D manager. Before joining Invarian, he was the Senior R&D engineer for System Design Division (High-Speed Team) of Mentor Graphics, where he was the project leader of PCB thermal analysis tool (HyperLynx Thermal) and also software developer of EMI DRC checker tool (Quiet Expert/HyperLynx DRC) for PCB design. Vladimir also served as R&D manager and technical leader of the timing and optimization group for Golden Gate Technology where he was responsible for the development of RC extraction, STA, SI and power analysis and also for timing and power optimization for IC physical design tool. He has also held Senior R&D engineer position with Synopsys, working for Physical Compiler and Clock Tree Compiler projects. He received his Master's of Science Degree at Moscow Institute of Physics and Technology, Moscow, Russia in 1997.
VP of Marketing and Business Development
Steve has over two decades of experience in both Silicon Valley and Wall Street. He has held various marketing and engineering roles in both publicly traded semiconductor companies as well as true startups. From corporate marketing Steve branched into the financial industry for a dozen years at various sell-side companies and was the owner of Sierra Tech Research, a firm whose clients were primarily New York Hedge Funds. Some of the corporate firms Steve has worked for include Radius, Chrontel, Oak Technology, ICS and IC Ensemble and his financial background includes time spent at Moors & Cabot, Hotovec Pomeranz and Sterling Financial before founding and running Sierra Tech Research for 8 years. Steve has a BSEE from San Jose State University and Series 7 & 63 Securities Licenses.