Aldec:Emulation Wiki

HES Components
HES™ is a complete ASIC/SoC hardware-based verification solution that provides a unified platform for bit level simulation acceleration, transaction level emulation, system architecture exploration, HW/SW co-verification, virtual modeling and prototyping.

Design Verification Manager (DVM™)
DVM is the main software of HES facilitating easy design setup and flexibility with its fully scriptable environment, ASIC to FPGA clock conversion, automatic design partitioning, advanced HDL compiler, incremental compilation and interface with commercial simulators. DVM is equipped with robust debugging features to help investigate and track down errors and bugs easily and quickly offering dynamic debugging with high visibility into the design, ability to set breakpoints and triggers, and ability to edit memory and register contents.

FPGA-Based Prototyping Boards
HES is fully customizable to interface with existing off-the-shelf or custom-in-house FPGA prototyping boards leveraging their performance, portability and low-cost benefits. Equipped with simulation acceleration and emulation capabilities, FPGA-based prototyping boards offer a high-speed and high-visibility debugging solution for ASIC/SoC verification.

Top Features

• Bit-Level Simulation Acceleration
  
• SoC HW/SW Co-Verification
  
• Transaction Level Emulation with SCE-MI 2.0, SystemC/C/C++, TLM2.0
  
• Extensive Debugging (static/dynamic probes, memory access using GUI & API)
  
• Fully Scriptable Environment
  
• RTL Simulator Interfaces: Active-HDL™, NC-Sim®, ModelSim®, Riviera-PRO™, QuestaSim® and VCS-MX®
  
• Off-the-shelf FPGA prototyping boards support (Aldec HES-5, Dini Group®, Synopsys® HAPS™)
  
• Custom-in-house FPGA prototyping boards support
  
• Virtual Modeling with Imperas® OVP™ and OVPsim™
  
• Linux and Windows® 32/64 bit support
  

What's New in DVM™