No. of masks used

[cyberakhil]

For a die containing billions of transistors...typically how many masks are used to the whole SOC to be photolithographed on Silicon

[Staf_Verhaegen]

For a die containing billions of transistors...typically how many masks are used to the whole SOC to be photolithographed on Silicon

Rule of thumb: #metals*2 + 20. For each metal layer you need a mask for the via layer and one for the metal layer. I think current nodes have 10 or more metal layers. The 20 extra masks is for poly, active area and all the well and diffusion implantation steps; also some masks for passivation but they are cheap. The exact number depends on the process and on the options used (low-Vt, triple well, ...).

[cyberakhil]

So I believe all these masks are created from the gds.. One quick question how are these masks created from the gds as in how is the footprint of the design translated on to the mask

[daniel_payne]

Here's a good presentation on going from GDS II to a mask: http://snf.stanford.edu/Process/Mask...cs-General.pdf

[Ginger Grant]

The number of masks is based on the technology the SOC is a product of. Here's a more interesting question: What is the number of steps in a process to produce a high yielding SOC?

[daniel_payne]

Elle,

I'll guess that there are hundreds to thousands of processing steps.

[Staf_Verhaegen]

Here's a more interesting question: What is the number of steps in a process to produce a high yielding SOC?

That will highly depend on what the definition of step is. One litho 'step' consists of 10-15 'substeps' (prime, coating, baking, illumination, development, measurements, ...).

greets,
Staf.

[Ginger Grant]

I was considering litho as a single step even though there is all the substeps involved. Yea.. talk about baking chips! Whew!

[Ginger Grant]

As for GDSII .. what you see is not what you get! The mask prep team will size up and down certain layers based on certain criteria all for purposes of conforming to manufacturability. It's really amazing that all this work actually produces a functioning circuit at the end of the day!

[Staf_Verhaegen]

I was considering litho as a single step even though there is all the substeps involved. Yea.. talk about baking chips! Whew!

The test chips I designed in my litho past were mostly going to metal1. If I remember correctly 100-120 lot turns were needed to get something working and measurable on metal1. This was for FINFET processing. Litho step is considered as 1 lot turn.

greets,
Staf.