Chasing Down Burn-in Failures

[chris_schuermyer]

When somebody has a burn-in (HTOL) failure during a product ramp, what is the usual procedure? I'm assuming that PFA is a big part, but are there other actions taken? Will a foundry accept responsibility and institute a corrective action? Will they know what corrective action needs to be taken? Will they need to collect more data? How owns the failure, a foundry or the fabless customer?

Chris Schuermyer
siliconyield.com

[clhende]

When somebody has a burn-in (HTOL) failure during a product ramp, what is the usual procedure? I'm assuming that PFA is a big part, but are there other actions taken? Will a foundry accept responsibility and institute a corrective action? Will they know what corrective action needs to be taken? Will they need to collect more data? How owns the failure, a foundry or the fabless customer?

Chris Schuermyer
siliconyield.com

Chris,

It's my experience that unless the failure occurs in their test chips/structures in the same manner as on the product dice, then the foundry will not accept responsibility. They might be happy to analyze it for them (as long as that is part of the contract), but they will be reticent to own the failure. Almost always, the fabless customer owns the failure consequences, as well as the reliability of the chip.

Best regards,

Chris Henderson
www.semitracks.com

[chris_schuermyer]

Chris,

It's my experience that unless the failure occurs in their test chips/structures in the same manner as on the product dice, then the foundry will not accept responsibility. They might be happy to analyze it for them (as long as that is part of the contract), but they will be reticent to own the failure. Almost always, the fabless customer owns the failure consequences, as well as the reliability of the chip.

Best regards,

Chris Henderson
www.semitracks.com

Hey Chris, thanks for the feedback! If a fabless customer is on the hook for reliability this would imply that the chip must be designed for reliability. Do you know if this is a common practice? This seems counterintuitive since the foundry usually provides the standard cell layouts. Also, is this what the whole field of antennae checks is aimed at?

[clhende]

Chris,

This is an important topic right now that many companies are grappling with. The bigger companies that utilize the foundries like Qualcomm, Broadcom, NVidia, etc. all have efforts underway, but they are nascent at best. The smaller companies are simply trying to get something to yield, so they tend to be more focused where your expertise lies (Yield Learning). Antennae checks are more aimed at reducing process-induced damage from Reactive Ion Etch processes to pattern the chip layers. The deposited charge can damage sensitive gates if one doesn't take precautions.

Best regards,

Chris Henderson
www.semitracks.com

[chris_schuermyer]

Chris,

This is an important topic right now that many companies are grappling with. The bigger companies that utilize the foundries like Qualcomm, Broadcom, NVidia, etc. all have efforts underway, but they are nascent at best. The smaller companies are simply trying to get something to yield, so they tend to be more focused where your expertise lies (Yield Learning). Antennae checks are more aimed at reducing process-induced damage from Reactive Ion Etch processes to pattern the chip layers. The deposited charge can damage sensitive gates if one doesn't take precautions.

Best regards,

Chris Henderson
www.semitracks.com

So when you say efforts underway, are you referring to design changes (Design for Reliability) or are you referring to foundry negotiations (feedback burn-in failures to the foundry so they can identify the root cause and correct for it in the process)?

Chris Schuermyer
siliconyield.com

[clhende]

Chris,

I am referring to design changes (Design for Reliability) activities at the fabless semiconductor houses, not foundry negotiations. Hope that helps.

Best regards,

Chris Henderson
www.semitracks.com

[jasicw]

Clhende:
when you mentioned design changes(Design for reliablity) activities, Is the front-end design(logic design) involved? in my mind, the DFR/DFM only are involved in backend design in form of DRC check. is my understanding correct?

thanks