You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!

Results 1 to 5 of 5

Thread: Verilog to System Verilog : A Successful journey towards SV

  1. #1
    Member Asic With Ankit's Avatar
    Join Date
    Apr 2012
    Posts
    29

    Verilog to System Verilog : A Successful journey towards SV

    Dear Readers,

    We have been using standard languages and methodologies for ASIC/FPGA design and Verification activities. We as an engineer must know on history of verification activities. Today we mostly work on verification standard languages like System Verilog. The whole industry is moving to accept this language with few methodologies (RVM, VMM, AVM, OVM, UVM etc...) as their standards for new and existing product development and verification.

    Now since we use the industry standard languages like VHLD, Verilog, and System Verilog, we must know and understand history and importance of Verification languages.

    Let’s understand how we reached to a System Verilog usage? What are the other different verification languages engineers were using in past few decades? How did they start their usage from Verilog to System Verilog for verification? Let’s go back to history and understand these questions.



    When Verilog first developed in mid-80, main requirement and usage of this language was to develop synthesizable RTL with not much complexity. Revolution started by late 1980s. By late 80s synthesis and simulation triggered a revolution for EDA industry. As time passed, In 90s industry realized a tremendous need to solve complex verification problems due to complex designs. This was the time when EDA Company played a key role in filling the requirement to solve this verification issues. Those days verification languages which become popular and people started using those were proprietary to some companies! Best examples are ‘Open Vera’ and ‘e’ language. Since these languages were proprietary to EDA companies, some people were using the Object Oriented Languages like C++. During those days some users were using Verilog to develop their testbench, looks interesting, Isn’t it!

    The problems gets started during 1990s when Verilog become an industry standard.

    In 1980s a company called Gateway Design Automation developed a logic simulator called Verilog-XL and Cadence acquired in 1989 with right. Now with a new strategy Cadence put the language in to the public domain with the intention that Verilog should become a standard. After this Verilog HDL is now maintained by Accellera a nonprofit making organization. In 1995 Verilog HDL became IEEE standard.

    Accellera came up with revised versions in 2001 and then in 2005 and industry taking this as standard and moved ahead.

    Accellera have also developed a new standard called ‘System Verilog’ which extends Verilog with newly added many feature with the concept of Object Oriented Programing. System Verilog then became an IEEE standard (1800-2005) in 2005.

    System Verilog is a super set of Verilog plus all the features known to be necessary for traditional verification. System Verilog is being used mostly in Verification activities because of higher level abstraction and user friendly features. Today System Verilog is already became a standard for Verification activities and most of the companies have started accepting his beauty! In addition to System Verilog usage and acceptance people have come up with few methodologies like (RVM, VMM, AVM, OVM, UVM etc…) With the addition of this type of methodologies Verification environments are becoming easy to handle, user friendly and most importantly the environments are becoming re-usable!

    Happy Reading!
    Ankit Gopani
    ASIC With Ankit



    Last edited by Daniel Nenni; 05-05-2013 at 05:41 AM.

  2. #2
    Top Influencer
    Join Date
    Nov 2010
    Location
    Silicon Valley USA
    Posts
    519
    A slightly different take on the history:

    VHDL was funded by the US government as part of the VHSIC program in the 80's - it has a bunch of problems that have never been fixed but is OK at the level of RTL and up. Verilog is better for actual Silicon sign-off, but was proprietary. Since VHDL was an open (if awful) standard, that put some pressure on Cadence to adopt VHDL or open up Verilog, so they created OVI and let it create the "open" standard. OVI morphed into Accellera and expanded on Verilog with Verilog-AMS and various other standards. The language Superlog was created by Co-Design ~ 2000 but wasn't getting a lot of traction so they decided to turn it into SystemVerilog through Accellera in the hope that making it an official standard would get them more customers (Intel being the only one they had). After being bought by Synopsys the Co-Design guys were largely replaced by Vera guys who had decided that the whole rubber-stamp of approval of a standards committee was a good idea, and just dropped a slightly morphed Vera on top of SV 1.0 and edited it until they ran out of time creating SV 2.0 (the folks in charge at Accellera wanting a new LRM to present at DAC each year), the results of that were then thrown over to the IEEE without much clean-up.

    IMO if Verilog had been open in the first place and we had just built up the bridges to C/C++ we would be a lot better off. My current job is working with VHDL and it sucks as badly now as it did 25 years ago, likewise Verilog has not actually improved at simulating anything in the same time frame - which is why the verification level keeps expanding to compensate. I see no swans among the ugly ducklings.

  3. #3
    Member Asic With Ankit's Avatar
    Join Date
    Apr 2012
    Posts
    29
    Thanks SimGuru for reading and adding valuable points on highlighting few more points on history.

    This is useful information.

    Regards,
    ASIC With Ankit

  4. #4
    Top Influencer
    Join Date
    Jan 2011
    Location
    The land of beer and chocolate
    Posts
    388
    Quote Originally Posted by simguru View Post
    I see no swans among the ugly ducklings.
    It seems you are not the only frustrated person . Look at Welcome to MyHDL [MyHDL]; a HDL language based on python. As I don't have experience myself I don't know at which scale in the ESL to RTL abstraction level this language fits.
    Trust me ...
    I know what I am doing.

  5. #5
    Top Influencer
    Join Date
    Nov 2010
    Location
    Silicon Valley USA
    Posts
    519
    Quote Originally Posted by Staf_Verhaegen View Post
    It seems you are not the only frustrated person . Look at Welcome to MyHDL [MyHDL]; a HDL language based on python. As I don't have experience myself I don't know at which scale in the ESL to RTL abstraction level this language fits.
    Unfortunately Python is very difficult to formally verify, so I'd stay away from it for high-level/hardware design. Same goes for Tcl/Perl/PHP etc. - most languages that are easy for humans to use are not good for machines to work with.

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •