Constrained Random Verification + and -

[gauravjalan]

In the last decade, adherence to Moore’s law demanded ‘divide and conquer approach’ for developing SoC/ASIC. The design cycle now requires develop/procure IPs; build sub systems using them and integrate these sub systems further to realize the final product. Some IPs (Networking protocols, Graphics, Video, DSP… etc) are complex enough that further division into blocks during design and verification is unavoidable. Amidst all this, verification still is the biggest challenge in meeting schedules and taping out bug-free products. The ever increasing design complexity problem has enabled rapid development in ASIC verification. From traditional directed verification approach to Constrained Random Verification (CRV), it has been a long way. CRV brought a paradigm shift in the way we verify our designs and enabled development of Coverage Driven Verification (CDV) and Standard methodologies (eRM, RVM, AVM, VMM, OVM & UVM). Click here to know the advantages and limitations of CRV.

[daniel_payne]

Is there any difference in choosing a VHDL, Verilog, System C or System Verilog simulator from Cadence, Synopsys or Mentor and then using the CRV approach?

[gauravjalan]

Daniel,

Yes, there is a difference. First one being the results will not be the same i.e. 10 random simulations giving required coverage on simulator is not reproducible on another. This is an interesting topic. Let me come up with a post

[daniel_payne]

It sounds like constrained random has similar traits to what ATPG is supposed to do: find low fault coverage areas, direct new stimulus to excite the area, then propagate results to the outputs.

[gauravjalan]

Hi Daniel,

Apologies for a late reply. Yes, the base is the same but the implementation and application varies a little.

Thanks & Regards,
Gaurav Jalan

[daniel_payne]

Gaurav,

Thank you, that makes sense to me then.