TSMC's 20nm process technology is 30 percent faster, has 1.9 times the density, and uses 25 percent less power than its 28nm technology. TSMC 20nm technology is the manufacturing process behind a wide array of applications that run the gamete from tablets and smartphones to desktops and servers.
The advanced 20nm technology demonstrates double digit 112Mb SRAM yield. The SRAM is a high performance device with second generation gate-last HKMG and third generation Silicon Germanium (SiGe) strain technology. Compared with 28nm technology, TSMC's 20nm process engages new Backend-of Line (BEOL) technology with >6% Keff reduction. Innovation and deep collaboration with customers provide the same scaling level as the past nodes. Technology and design innovation keep production costs in check. In addition, multiple customers' IP have been verified on 20nm test chips.
Empowered by TSMC's Open Innovation PlatformR (OIP) design ecosystem, designers can optimize their 20nm designs with qualified IP, design tools and methodologies, including flows for innovative patterning technology. Lithography techniques must change at the 20nm node to surmount inherent resolution challenges. TSMC has made this task transparent through our work and collaboration with leading EDA companies. The tools now support built-in technologies that comprehensively cover every design stage for designers to implement 20nm designs with minimum modifications to existing methodologies or flows.
As work continues to reach final 20nm certification in 2012, TSMC is supporting both EDA vendors and IP suppliers with design enablement kits. These kits facilitate continuous improvement and interaction between designers, the foundry; and tool and IP suppliers to prepare the 20nm design ecosystem for production success.
The design ecosystem includes robust Design for Manufacturing (DFM) solutions, Process Design Kits (PDKs), foundry design rules, foundation library and IP, third-party IP, EDA tools, design reference flows and design services.