Formal basis for characterizing and comparing commercially available FPGAs.

[alexberka]

Two years ago the ultra fine grained formal model for reconfigurable computing called the Synchronic A-Ram was introduced, which has unit time propagation delay between any two locations in memory. Formal models are abstracted from physical considerations, and usually have some characteristic that is physically implausible: the Turing machine performs instruction fetch in unit time regardless of the size of the instruction table, and lambda calculus performs beta reduction in one step regardless of the length of the expression.

Propagation delay may be introduced into the Synchronic A-Ram descriptions of FPGAs however, if the physical components of real architectures; logic blocks, switch blocks and wire segments etc are accurately represented in terms of the model’s fine grained primitive instructions. The amount of time required for a signal to pass through a succession of FPGA wire segments will be reflected in a Synchronic A-Ram program that accurately describes the wire segments, without any modification to the model.

Data transfer from one end of an FPGA wire segment to the other occurs in constant time, which would correspond to the constant time for the transfer of that wire segment in the Synchronic A-ram model. Consequently there is the prospect of the formalization of timing and logic operations in FPGA architectures in terms of a simple semantic model, and a formal basis for comparing them. To achieve that formalization however, access would be required to sufficiently detailed description down to the logic gate level of the architectures offered by Xilinx, Altera, Lattice Semi etc..

May I ask if anyone knows of some public repository where such descriptions are easily available without having to trawl through patent libraries, or is it the case that some aspects of designs are considered too commercially sensitive to reveal?

[daniel_payne]

The FPGA vendors protect the transistor-level schematics and IC layout of their cells, blocks, modules and architecture. Under NDA the FPGA companies will divulge such details to EDA vendors that provide logic synthesis tools for example.

Here are some links that may be helpful to you:

Field-programmable gate array - Wikipedia, the free encyclopedia

http://www.eecg.toronto.edu/~jayar/p...own/survey.pdf

http://www.altera.com/literature/wp/wp-01003.pdf

http://www.actel.com/documents/Actel...tecture_AN.pdf

[alexberka]

Hi Daniel, thanks. There might be a way to access only the information needed for abstract comparisons, without compromising sensitive IP. Some of the links you mention are somewhat introductory, if that is all that can be hoped for in terms of detail, then perhaps this idea cant proceed.

[Staf_Verhaegen]

Here are some links that may be helpful to you:

Googling for bistream reverse engineering (https://www.google.com/search?q=bits...se+engineering) could give you more insight in the internals of FPGAs.
Be aware that legality of reverse engineering is much dependent on where you are located.

greets,
Staf.

[alexberka]

Thanks for the heads up Staf.

Thinking about it, a netlist does not normally include wire distances, which might be needed. The FPGA companies would have to want to cooperate, for this to work. Hmm.

[alexberka]

It has been pointed out to me I should have provided a link to the material, apologies.

http://www.isynchronise.com/Isynchro..._files/ssc.pdf

[alexberka]

As a courtesy I would like to mention there is a bit of extra discussion at

Formal basis for characterizing and comparing commercially available FPGAs. | LinkedIn

[daniel_payne]

Have you tried to contact the FPGA vendors directly?

If you are part of an EDA company then they would have a compelling reason to comply.

Some FPGA schematics in this PDF: http://www.pearsonhighered.com/sampl...0131424610.pdf

[alexberka]

Have you tried to contact the FPGA vendors directly?

Thanks for the link Daniel, it looks promising. Its too early to knock at the vendors doors just yet. There was a contribution in the other discussion that suggested applying asymptotic complexity measures to models of FPGAs would probably not be fruitful, because the order of magnitude bounds that might be arrived at are too blunt to usefully differentiate them. The kind of comparison I was initially thinking of really belongs to the realm of performance evaluation. My intuition was that giving a common simple semantics to a range of FPGAs should make possible novel comparisons, and will ponder alternative potential pay-offs.