The Problems with SoC IP Integration

[CharlieD]

IP integration continues to delay our designs. Is there really such a thing as reusable IP? Or is that just a marketing sound bite? Lets start a list of problems with IP integration and brainstorm solutions. We can make it into a Wiki for future reference.



SoC IP Integration Problems:

1. How do you fix IP timing problems post P&R when you didn't design it? Is that timing path real? What is in that black IP box?
2. IP SDC constraints are different for each design. How do you account for that?
3. ?

[simguru]

For mixed signal IP that is sensitive to it's environment, e.g PLLs, you need to hand over layout (& Spice level netlist). It would be a lot easier (from the sales side) if you could publish behavioral models that do the same job and have some verification (of usage) built-in and a "black box" layout. Unfortunately there is no way to back-annotate such models.

[DaveW]

Life would be easy if everybody used the same system architecture, performance constraints and silicon technology. However, products would not be differentiated! User must expect to do some work 'around the edges' to integrate IP into their own unique design. Do users really expect IP to just 'drop in' these days? Part of the 'due diligence' process is figuring out what integration issues there might be.

[SunnyLining]

I like the Wiki idea. In fact, I think it should be a subthread of a general system integration wiki. There could also be pre- and post-silicon threads; digital, analog, and mixed-mode threads; etc.

System integration just allows a whole new level of problems to crop up you never thought of. An experienced system integrator can think of issues in a design review you never even thought of that make you think, "Well, there goes that spin." Not that such a serious blunder ever happened to me or anything .

[dcblack]

DaveW

User[s] must expect to do some work 'around the edges' to integrate IP into their own unique design.

Work around the edges yes, but some of today's IP goes much deeper than just the edges. In the past, we used complete devices, LSI and VLSI components, which came with detailed datasheets describing timing, power and functionality. Today's complex designs need more details including behavioral (or TLM) models and embedded software that include features to help with analysis and debug. The concept of built-in usage checks (verification) by simguru is an excellent idea. High level models could have features to validate the application.

[troyhicks]

Does anyone know if there's been any follow-on work to the QIP proposal from VSIA in 2008?

[simguru]

When VSIA folded some stuff moved to Accellera, but I'm not sure there has been much follow on work - in theory I'm on the e-mail lists, but have not seen anything in ages.

[kencweng]

IMO, the IP users should be fully responsible for the problems with SOC integration of IP. IP quality does not come for free. In a way, the IP industry is not "regulated". Any IP provider can do and say whatever it wants. I strongly believe the concept of free market. Just the mechanism for "check and balance" for IP industry is not exisiting.

I agree that we should not fix the timing problem. But, there should be a way to prevent the timing problem before you use the IP.

IP integration continues to delay our designs. Is there really such a thing as reusable IP? Or is that just a marketing sound bite? Lets start a list of problems with IP integration and brainstorm solutions. We can make it into a Wiki for future reference.



SoC IP Integration Problems:

1. How do you fix IP timing problems post P&R when you didn't design it? Is that timing path real? What is in that black IP box?
2. IP SDC constraints are different for each design. How do you account for that?
3. ?

inShare0

[klg]

You may consider to use the free SoC platform integration tool named Baya listed in the website - Free Miscellaneous EDA Utilities in Java