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Thread: Old and New IP in Zynq

  1. #11
    Blogger Luke Miller's Avatar
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    Hi, just a quick suggestion, try looking into a hardware prototyping environment and map bit by bit if you will. Check out Zedboard. Mine is coming soon and will be trying all sorts of , well interesting things.
    My apologies as I have not read the other replies if this a repeat.
    Best
    LM
    Regards,
    Luke Miller
    theFPGAexpert.com

  2. #12
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    james kennedy • Respectfully, this is an interesting problem. Is there room in the Zynq Artix fabric for your entire design? Is the task to connect your design to the Processor System ARM cores? I'm also looking at optimal ways to get data between PS and PL (Programmable Logic). There are the different AXI interfaces to custom IP. I'm also looking at using DMA to/from BRAM.

  3. #13
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    Tryggve Mathiesen • I have worked with some projects moving from MicroBlaze to Zynq.
    Before reusing too much bus complexity, try to use the native AXI buses in Zynq.
    The high performance memory interface (x4 32/64 bit) with fifos built in can be a good
    replacement of MPMC/DDR memory interfaces from MB design.
    Make sure to move peripheral interfaces from the MB design into the hard Zynq peripherals, thus you save a lot of logic in the PL section.
    Consider changing you design with DMA controllers in logic and make use of the hard
    DMA units in the PS section. At last FSL links matches AXI streaming bus well.
    Simple AXI Lite interface can replace most PLB slave interface, avoid bridges.
    Good luck!

  4. #14
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    Hi Bengt,

    I'm not sure from your post whether you are looking for help on the hardware design or the system/software side of things. If help is needed with the system/software, a virtual prototype is a good way to go, as John Swan previously suggested. With virtual prototyping tools and environments, there are different factors to look at, and rate the importance to your project. Ease of creating the virtual prototype, including availability of processor models, is one factor. The second key factor is what tools are available to run on the virtual prototype. This ranges from debuggers, like standard GDB for software debug, to the hardware-software co-debug (makes peripheral model and associated driver development much easier), to tools specifically for embedded software development and test. The third key factor is the trade-off between simulation accuracy -- from cycle accurate to instruction accurate -- and performance. There is anywhere from 3 to 5 orders of magnitude difference in simulation performance depending on where you are in the accuracy spectrum.

    Certainly I am writing this from the perspective of someone in this business, as I work for Imperas. You might also check out our Open Virtual Platforms (OVP) technology for building virtual prototypes.

    Good luck with your project,

    Larry

  5. #15
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    Zynq

    Quote Originally Posted by LinkedIn View Post
    james kennedy Respectfully, this is an interesting problem. Is there room in the Zynq Artix fabric for your entire design? Is the task to connect your design to the Processor System ARM cores? I'm also looking at optimal ways to get data between PS and PL (Programmable Logic). There are the different AXI interfaces to custom IP. I'm also looking at using DMA to/from BRAM.

    Interesting it is James, Need to make it fit and yes we need to connect design to Processor system ARM core. I hope to be able to get back to you later with some more details of how it ended, looks OK right now.

    Regards
    Bengt

  6. #16
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    Quote Originally Posted by LinkedIn View Post
    Tryggve Mathiesen • I have worked with some projects moving from MicroBlaze to Zynq.
    Before reusing too much bus complexity, try to use the native AXI buses in Zynq.
    The high performance memory interface (x4 32/64 bit) with fifos built in can be a good
    replacement of MPMC/DDR memory interfaces from MB design.
    Make sure to move peripheral interfaces from the MB design into the hard Zynq peripherals, thus you save a lot of logic in the PL section.
    Consider changing you design with DMA controllers in logic and make use of the hard
    DMA units in the PS section. At last FSL links matches AXI streaming bus well.
    Simple AXI Lite interface can replace most PLB slave interface, avoid bridges.
    Good luck!
    Thanks for your great hands on recommendations Tryggve, will for sure take this into account moving forward !

    Regards
    Bengt

  7. #17
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    I have to say that this group's willingness and helpfulness is outstanding ! Thanks to everybody for your great suggestions ! I hope to be able to post an update by late summer of how things did turn out and how we solved some of these difficult design tasks.

    Best Regards
    Bengt

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