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Thread: Wally Rhines 3D IC Keynote

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    Blogger Paul McLellan's Avatar
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    Wally Rhines 3D IC Keynote

    I went to Wally Rhines keynote presentation on 3D ICs at the GlobalPress event in Santa Cruz a few weeks ago. As usual for a Wally keynote, it was long on data and largely focused on what EDA as a whole is up to rather than pushing any particular Mentor-specific solutions. Here’s my summary (and to keep it readable I haven’t preceded each paragraph with “Wally thinks…”). I’ll focus on the nearer term since it is clearer to see a short way through the fog. Wally’s view is that true 3D chips (meaning TSVs in active areas of stacks of more than 2 die) is at least 5 years out and is not an incremental development from where we are today (not just for EDA but also for manufacturing).

    Also, see the 3D IC wiki for definitions of terms etc.

    The bottom line is that in the long run, cost advantages will eventually drive 3D-IC system ICs. Historically, learning curve cost reduction was driven by scaling, of course, but we are starting to fall off that cost curve.


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    The increasing use of double patterning makes it hard to keep wafer costs decreasing by much more than 15% per node at 22nm and 15nm, compared with nearly 50% at 90nm. Most likely there will be no improvement in silicon-area/hour/capital-$ going forward.
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    So the third dimension is going to have to make up for lack of cost reduction through scaling. This is already starting to happen in memory, with memory stacks and package-in-package with processor and memory (e.g. Apple’s A4 and A5 chips).


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    So, in the long run, cost will drive systems to 3D, but the long run will likely be a long time coming. In the meantime, early adoption will be driven by performance, power and form factor (size) when the differentiation can support a higher price.



    • Performance: much higher bandwidth between chips inside the same package. Shorter wire lengths, shorter critical paths.
    • Power: reduce L and C, shorter interconnect paths, no need for traditional I/O drivers
    • Mixed-die technologies: heterogeneous technologies, mixed generations
    • Smaller: reduced area, thickness (portable devices).



    Through silicon vias (TSVs) reduce memory I/O power consumption by 75% (per Micro News 2/28/2011) and that is comparing true 3D chips with package-on-package designs, the savings versus separate packages on a conventional PCB would be greater still.
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    In the short term, for anything other than memory (and camera imaging) the most attractive technology is 2.5D, the silicon interposer. Here no TSVs are pushed through active area, instead conventional chips are flipped onto a silicon substrate called an interposer. Xilinx have done this for the 28nm arrays, managing to get good yields and doubling FPGA capacity with a 50% power reduction versus what they could get from 40nm. In total, this is a 100X improvement in interdie bandwidth/watt.
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    So 2.5D should provide a long, cost-effective transition to true 3D, not least because there are major manufacturing issues with TSVs in active areas (keep out blocking, stress related threshold shifts and other things) not to mention it requires a full retooling of the EDA tool flow which doesn’t yet exist. In addition you get many of the advantages of 3D (mixing die, smaller sizes etc) so this solution will likely last longer than a lot of people expect.


    The design methodology for 2.5D is evolutionary from what we do today. After all, apart from the interposer the chips are pretty “normal” and so can be done with standard 2D tools. Yes, there are some issues in test, some in extraction, thermal analysis is more complicated. But, by and large, with some incremental addition to existing 2D tools (which all the EDA suppliers are already working on, none of which require any technological breakthroughs) 2.5D designs can be done.


    Full 3D design is not incremental from where we are today, especially once lots of die can be stacked to form a single system (for example, vertical dataflow down through the die stack). There are big impacts on delay calculation within the design, there are big TSV induction effects, inter-die variation can be horrible to handled, and the thermal issues start to be very complex since there are parts of some die buried deep inside what is pretty much a cube of silicon.


    There is a lot of work going on to standardize various aspects of 3D-IC design but, as with any standardization, you can only standardize something once you know how to do it well.
    So where do we stand: today we have sensors on logic (CCD flipped onto camera chips etc), we have limited volume stacked memory, and we have package-on-package and memories flipped onto processors.


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    The next 2-3 years will see rapidly increasing use of interposers for 2.5D designs. Mixed analog, RF, logic and memory in multi-die stacks. TSVs will be kept out of active circuitry (i.e. at edge of chips). Standards will make it possible to mix die from different vendors.

    True embedded TSV in leading edge logic chips is at least 5 years out. Then we will start to see mixed stacks but with TSVs spread across the die, not pushed out into an extra “padring”.
    Last edited by Daniel Nenni; 04-21-2011 at 04:38 PM.

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