You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!

Results 1 to 7 of 7

Thread: Power consumption of IP during long soft resets

  1. #1
    Member
    Join Date
    Nov 2012
    Posts
    2

    Power consumption of IP during long soft resets

    Hi,
    It just popped over my mind what will be the power consumption impact during soft reset is set by s/w for long duration and not clearing it.
    Some of our IPs use the soft reset pin OR'd with power on reset and it will hold the reset pin of all the flops till software clears this bit.
    All the clocks will be running so i am worried on the power consumption impact in cases where the s/w doesn't clear this bit immediately?

    Can any of you guys share your thoughts on this.

    Regards,
    Satya

    Last edited by Daniel Nenni; 04-25-2013 at 07:30 AM.

  2. #2
    Blogger Daniel Payne's Avatar
    Join Date
    Sep 2010
    Location
    Tualatin, OR
    Posts
    1,833
    Satya,

    You can simulate this condition in your HDL simulator and then estimate the power consumption impact with tools like PowerArtist from Apache.

    How are you estimating power with EDA tools today? Are you designing an FPGA or SoC?
    Daniel Payne, EDA Consultant
    www.MarketingEDA.com
    503.806.1662

  3. #3
    Member
    Join Date
    Nov 2012
    Posts
    2
    Hi Daniel,

    We are targeting SoC and for power estimation we use the PTPX during post layout. Haven't tried PowerArtist yet. However i was wondering if any of you faced such scenario.

  4. #4
    Member
    Join Date
    Jan 2013
    Posts
    2
    Satya,
    You may need to ascertain from the IP designers if they are gating the clocks on the flops when at reset, and how the flops are getting reset. Gating of flops is one method used by designers to save power.
    Regards

  5. #5
    Influencer gauravjalan's Avatar
    Join Date
    Jan 2011
    Location
    Bangalore, India
    Posts
    45
    Satya,

    Why would the SW keep soft reset in set state for a long time? If this is just a thought and you want to analyze it, you can always create a VCD and pass it to PTPX for this period and collect power numbers. If clocks are toggling, the ckt will experience quite high power (Dynamic + Leakage). If such a case needs to be avoided in hardware the designer may want to gate clocks or if the period is quite long and power domains are defined, you may even plan to turn off the circuit.

    If the controls from HW are available, it is highly likely that SW will try to minimize power by programming relevant bits.

  6. #6
    Member Jean-Yves Oberlé's Avatar
    Join Date
    Apr 2013
    Posts
    2
    Satya,

    Just to reinforce Gauravjalan's feedback, getting a VCD from the reset period and read it in PTPX is probably the most straightforward approach. Experience also showed me that it is a good practice to verify that reset state of the flops is properly modeled in the .lib files regarding power consumption (either by having a look directly in some .lib files or by correlating with SPICE simulations for two or three flops).

    Best regards.

  7. #7
    Member
    Join Date
    Mar 2012
    Posts
    2
    Hi Satya,
    As long as the flip-flops are properly characterized in the Liberty file (with both internal power and leakage being state dependent), you should be able to accurately measure the impact of the soft reset which is not properly deasserted, even at RTL. If the amount of wasted power is high and if you believe there is a risk this scenario may occur in the real application, it is possible to introduce safeguards in the hardware. As explained by Venkataraman and gauravjalan, this can consist of introducing clock gating. You could use the reset signal as a condition of course but it is probably better to use self gating techniques (with XOR or OR gates) which could also reduce power outside of reset. Performing a differential power analysis on the modified RTL should help in deciding if the newly introduced optimizations are actually worth it (there is basically a compromise between reduce dynamic power and increased leakage). Hope this helps.
    Best regards.

Tags for this Thread

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •