Design for verification is defined differently by EDA vendors and other stake holders. The clearest definition you can find comes from synopsys: “the purpose of DFV is to leverage a designer’s intent and knowledge to strengthen the verification effort”. This definition calls for a clear articulation of the design intent by the designer. The definition further calls for “maximizing the correctness of functionality of individual modules” and for “Ensuring the correctness of integration of these modules”. As those requirements indeed define DFV in a compelling way, it is the implementation of them in current design and verification flows which does not lead to the required result where the design is clean and ready for integration.
The above definition requires some of the block verification work, such as assertion definition, to be done upfront by the designer at an early stage of the development process. Although it may sound simple and straight forward, this kind of effort seldom fits with chip project schedule and the extra effort cannot be justified when the pressure is to finish the design stage and allow other critical downstream work to start. The verification engineer given the task of checking the block is therefore overwhelmed with low level bugs and fails to concentrate on the high level block functionality and its integration into the chip level.
Proposing to solve this prevalent scenario, the RMM (Reuse Methodology Manual) suggests that “companies have set up internal development groups dedicated to developing reusable blocks”. This may be correct for some of the large design IPs that may be re-used in multiple projects, but not for low level modules affecting the block level verification effort.
The same principles used for large IP blocks, that are either developed by separate teams or bought from third party, can be applied to the low level generic components. If those components abide by the above design for verification, their correctness is maximized, their integration is simple and their behavior is well defined, the benefits to verification effort may be very significant.
An example block:
All the blocks in red could potentially be pre-designed and pre-verified saving many test cases and enabling the verification to concentrate on the central block where the impact on the overall functionality of the device is most critical.
The question to ask is, why treat the large IP blocks different than the low level generic portions that may repeat many times in each device?