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Thread: Best Low Power techniques around !!!

  1. #31
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    Switching activity in the interconnects cause a lot of power consumption. Some encoding like T0 is used to avoid unnecessary switching activity on the interconnect.

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  2. #32
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    Motoi ICHIHASHI Can I add a comment?

    At first, I suppose we should consider which part of power consumption we want to reduce; Dynamic power or Static power, and which design level we can use.
    Here, I would like to discuss the list of some "low-power" technique within the CMOS technology. (Now besides the trade off)

    Dynamic power save technique:
    Algorithm: State encoding, Operand isolation, Pre-computation
    Physical design / RTL: Re-timing, Clock gating
    Performance control: DFS
    + Voltage control: DVS, DVFS, Dual VDD, Multi power supplies
    + Variability compatibility: AVS

    Static power save technique:
    Algorithm: State dependent leakage reduction
    Physical design / RTL: Device channel bias, Long channel standard cell optimization
    Voltage control: MTCMOS, Power gating, SC-CMOS

    Dynamic & static power save technique:
    Physical design ./ RTL: Multi-Vt cell synthesis
    + Variability compatibility: GALS
    Voltage control + Vt control: Variable threshold biasing,
    + Variability compatibility: Vt optimization

    It is so sad that I can't show you the graphical list table here.
    Indeed, I extracted this one from my thesis. I'm very appreciate it if you add your comments on this thread.

    Thanks,

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  3. #33
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    The best low power design book was written by Dr. Chandrakasan and Dr. Brodersen
    in 1995. They explained architectural approaches to low power long before EDA companies showed up with low power tools.
    Posted by Tim

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  4. #34
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    FYI - Here's the above mentioned Low-Power CMOS Design book at Amazon.com

    This collection of important papers provides a comprehensive overview of low-power system design, from component technologies and circuits to architecture, system design, and CAD techniques. LOW POWER CMOS DESIGN summarizes the key low-power contributions through papers written by experts in this evolving field.

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    Daniel Payne, EDA Consultant
    www.MarketingEDA.com
    503.806.1662

  5. #35
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    Isscc 2012

    Look for a major announcement from AMD at ISSCC 2012 in SF about a new and very
    unique way to reduce power ... it's called resonant clock mesh design. Better
    performance, BIG reduction in power ... it's worth knowing about. Here's
    the listing from ISSCC 2012:

    3.7 Resonant Clock Design for a Power-Efficient High-Volume x86-64 Microprocessor
    V. Sathe(1), S. Arekapudi(2), A. Ishii(3), C. Ouyang(2), M. Papaefthymiou(3,4), S. Naffziger(1)
    (1) AMD, Fort Collins, CO (2) AMD, Sunnyvale, CA
    (3) Cyclos Semiconductor, Berkeley, CA; (4) University of Michigan, Ann Arbor, MI

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