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			<title>RSoft Design Group acquired by Synopsys</title>
			<link>http://www.semiwiki.com/forum/f2/rsoft-design-group-acquired-synopsys-1563.html</link>
			<pubDate>Wed, 09 May 2012 19:49:25 GMT</pubDate>
			<description>EE Times...</description>
			<content:encoded><![CDATA[<div><a href="http://www.eetimes.com/electronics-news/4372595/Synopsys-buys-photonics-design-tool-firm-?cid=NL_EETimesDaily" target="_blank">EE Times</a> reported this acquisition today, and we've added it to our <a href="http://www.semiwiki.com/forum/showwiki.php?title=Semi+Wiki:EDA+Mergers+and+Acquisitions+Wiki&amp;redirect=no" target="_blank">Wiki page of all known EDA mergers</a>.</div>

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			<category domain="http://www.semiwiki.com/forum/f2/">SemiWiki</category>
			<dc:creator>daniel_payne</dc:creator>
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			<title>Verification claims 70% of the chip design schedule!</title>
			<link>http://www.semiwiki.com/forum/f209/verification-claims-70%25-chip-design-schedule-1557.html</link>
			<pubDate>Mon, 07 May 2012 03:02:19 GMT</pubDate>
			<description>Human psychology points to the fact that constant repetition of any statement registers the same into sub-conscious...</description>
			<content:encoded><![CDATA[<div>Human psychology points to the fact that constant repetition of any statement registers the same into sub-conscious mind and we start believing into it. The statement, “Verification claims 70% of the schedule” has been floating around in articles, keynotes and discussions for almost 2 decades so much that even in absence of any data validating it, we believed it as a fact for a long time now. However, the progress in verification domain indicate that this number might actually by a "FACT".<br />
 <br />
20 years back, the designs were few K gates and the design team verified the RTL themselves. The test benches and tests were all developed in HDLs and sophisticated verification environment was not even part of the discussions. It was assumed that the verification accounted for roughly 50% of the effort. <br />
 <br />
Since then, the design complexity has grown exponentially and state of the art test benches with lot of metrics have pre empted legacy verification. Instead of designers, a team of verification engineers is deployed on each project to overcome the cumbersome task. Verification still continues to be an endless task demanding aggressive adoption of new techniques quite frequently. <br />
 <br />
A quick glance at the task list of verification team shows following items –<br />
- Development of metric driven verification plan based on the specifications.<br />
- Development of HVL+Methodology based constrained random test benches.<br />
- Development of directed test benches for verifying processor integration in SoC.<br />
- Power aware simulations.<br />
- Analog mixed signal simulations. <br />
- Debugging failures and regressing the design.<br />
- Add tests to meet coverage goals (code, functional &amp; assertions).<br />
- Formal verification. <br />
- Emulation/Hardware acceleration to speed up the turnaround time.<br />
- Performance testing and usecases.<br />
- Gate level simulations with different corners.<br />
- Test vector development for post silicon validation.<br />
 <br />
The above list doesn’t include modeling for virtual platforms as it is still in early adopter stage. Along with the verification team, significant quanta of cycles are added by the design team towards debugging. If we try to quantify the CPU cycles required for verification on any project, the figures would easily over shadow any other task of the ASIC design cycle.<br />
 <br />
Excerpts from the <a href="http://blogs.mentor.com/verificationhorizons/blog/author/hfoster/page/2/" target="_blank">Wilson Research study</a> (commissioned by <a href="http://www.mentor.com/" target="_blank">Mentor</a>) indicate interesting data (approximated) –<br />
- The industry adoption of code coverage has increased to 72 percent by 2010. <br />
- The industry adoption of assertions had increased to 72 percent by 2010. <br />
- Functional coverage adoption grew from 40% to 72% from 2007 to 2010.<br />
- Constrained-random simulation techniques grew from 41% in 2007 to 69% in 2010.<br />
- The industry adoption of formal property checking has increased by 53% from 2007 to 2010.<br />
- Adoption of HW assisted acceleration/emulation increased by 75% from 2007 to 2010.<br />
- Mean time a designer spends in verification has increased from an average of 46% in 2007 to 50% in 2010.<br />
- Average verification team size grew by a whopping 58% during this period.<br />
- 52% of chip failures were still due to functional problems.<br />
- 66% of projects conitnue to be behind schedule. 45% of chips require two silicon passes and 25% require more than two passes. <br />
 <br />
While the biggies of the EDA industry are evolving the tools incessantly, a brigade of startups has surfaced with each trying to check this exorbitant problem of verification. The solutions are attacking the problem from multiple perspectives. Some of them are trying to shorten the regressions cycle, some moving the task from engineers to tools, some providing data mining while others providing guidance to reduce the overall efforts.<br />
<br />
The semiconductor industry is continuously defining ways to control the volume of verification not only by adding new tools or techniques but redefining the ecosystem and collaborating at various levels. The steep rise in the usage of IPs (e.g. ARM’s market valuation reaching $12 billion, and Semico reporting the third-party IP market grew by close to 22 percent) and VIPs (read posts <a href="http://whatisverification.blogspot.in/2012/02/verification-ip-changing-landscape-part.html" target="_blank">1</a>, <a href="http://whatisverification.blogspot.in/2012/02/verification-ip-changing-landscape-part_26.html" target="_blank">2</a>, <a href="http://whatisverification.blogspot.in/2012/03/choosing-right-vip.html" target="_blank">3</a>) is a clear indicative of this fact.<br />
<br />
So much has been added to the arsenal of verification teams and their ownership in the ASIC design cycle that one can safely assume the verification efforts having moved from 50% in early 90s to 70% now. And since the process is still ON, it would be interesting to see if this magic figure of 70% still persist or moves up further!!!<br />
<br />
<br />
<br />
Cheers!!!<br />
<a href="http://www.blogger.com/profile/16509909311582718412" target="_blank"><font color="#417394">Gaurav Jalan <br />
 </font></a>Connect with me @ <a href="http://in.linkedin.com/in/gjalan" target="_blank"><font color="#417394">http://in.linkedin.com/in/gjalan</font></a></div>

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			<category domain="http://www.semiwiki.com/forum/f209/">Verification</category>
			<dc:creator>gauravjalan</dc:creator>
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			<title><![CDATA[imec's annual report 2011]]></title>
			<link>http://www.semiwiki.com/forum/f2/imecs-annual-report-2011-a-1551.html</link>
			<pubDate>Fri, 04 May 2012 09:16:33 GMT</pubDate>
			<description>A post for these people who want a little insight in what happens behind the scene on technology development before the...</description>
			<content:encoded><![CDATA[<div>A post for these people who want a little insight in what happens behind the scene on technology development before the big press releases (like Intel's 3D-transistor or HP's memristor [*]).<br />
My <a href="http://www2.imec.be/be_en/home.html" target="_blank">company</a> - actually a non-profit research institute - has published a nice <a href="http://annualreport.imec.be" target="_blank">annual report</a> for 2011.<br />
<br />
enjoy,<br />
Staf.<br />
[*] For clarity: Intel is an imec partner, HP is not <acronym title="As far as I know">AFAIK</acronym> but imec does do research on resistive RAM and a memristor is a kind of resistive RAM.</div>

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			<category domain="http://www.semiwiki.com/forum/f2/">SemiWiki</category>
			<dc:creator>Staf_Verhaegen</dc:creator>
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			<title>Who will Apple partner with at 20nm: TSMC, Intel, Both, or Neither?</title>
			<link>http://www.semiwiki.com/forum/f2/who-will-apple-partner-20nm-tsmc-intel-both-neither-1540.html</link>
			<pubDate>Tue, 01 May 2012 01:28:32 GMT</pubDate>
			<description>Ever since Intel announced plans to offer foundry services at 22nm speculation has run rampant on whether Apple will...</description>
			<content:encoded><![CDATA[<div>Ever since Intel announced plans to offer foundry services at 22nm speculation has run rampant on whether Apple will move from Samsung to Intel or TSMC. I think it is a given Apple will, at a minimum, second source wafers as a result of the product conflict with Samsung. Second sourcing also gives Apple bargaining power and the opportunity to work with leading edge silicon.<br />
<br />
The question is who will win Apples 20nm business? I must recuse myself but let us take a vote and see if the crowd is right once again.<br />
<br />
D.A.N.<br />
<br />
<script src="//platform.linkedin.com/in.js" type="text/javascript"></script><br />
<script type="IN/Share"></script></div>

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			<category domain="http://www.semiwiki.com/forum/f2/">SemiWiki</category>
			<dc:creator>Daniel Nenni</dc:creator>
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		<item>
			<title>Intel say fabless model collapsing... really?</title>
			<link>http://www.semiwiki.com/forum/f2/intel-say-fabless-model-collapsing-really-1530.html</link>
			<pubDate>Fri, 27 Apr 2012 08:21:09 GMT</pubDate>
			<description><![CDATA[Hello colleagues on Semiwiki 
 
I'm a newbie here but keen to extend my network out from the UK. I came across this...]]></description>
			<content:encoded><![CDATA[<div>Hello colleagues on Semiwiki<br />
<br />
I'm a newbie here but keen to extend my network out from the UK. I came across this headline reported in EETimes (<a href="http://www.eetimes.com/electronics-news/4371617/Intel-exec-says-fabless-model--collapsing-" target="_blank">Intel exec says fabless model</a> ) and I wondered what everyone else thought about it. If you follow it to a logical conclusion it suggests only Intel will be able to make chips, the IDM model wins out yet its full of paradox and contradiction (of course). Any comments?<br />
<br />
John<br />
<a href="http://www.nmi.org.uk/index" target="_blank">NMI</a><br />
<br />
<script src="//platform.linkedin.com/in.js" type="text/javascript"></script><br />
<script type="IN/Share"></script></div>

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			<category domain="http://www.semiwiki.com/forum/f2/">SemiWiki</category>
			<dc:creator>JohnMoor</dc:creator>
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			<title><![CDATA[Demystifying Analog & Mixed-Signal ASICs]]></title>
			<link>http://www.semiwiki.com/forum/f141/demystifying-analog-mixed-signal-asics-1527.html</link>
			<pubDate>Thu, 26 Apr 2012 21:59:52 GMT</pubDate>
			<description>When considering a new ASIC design, carefully consider the role Analog will play in its deployment. To minimize risk,...</description>
			<content:encoded><![CDATA[<div>When considering a new ASIC design, carefully consider the role Analog will play in its deployment. To minimize risk, choose your ASIC development partner carefully.Most of the time, non-critical Mixed-signal ASIC design skills (meaning an ability to cut and paste functional blocks from a cell library)  will be sufficient. <br />
<br />
For those applications when the Analog performance is critical, you need to minimize your risk. Custom Analog Design is the only way to assure your product's peak performance.  Always  seek out an Analog ASIC partner with the right Analog design skills and experience to match the application. To help you understand the benefits of a full custom apporach, go to <a href="http://www.jvdinc.com/whitepapers.php" target="_blank">JVD, Inc. : Whitepapers : ASIC Design, Manufacture and Test</a></div>

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			<category domain="http://www.semiwiki.com/forum/f141/">AMS Design</category>
			<dc:creator>Bob Frostholm</dc:creator>
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			<title>hi everyone. I need a advice.</title>
			<link>http://www.semiwiki.com/forum/f2/hi-everyone-i-need-advice-1522.html</link>
			<pubDate>Wed, 25 Apr 2012 09:20:28 GMT</pubDate>
			<description>I want to go Masters program of microelectronics. Which university to choose? Or recomended professor (email etc). 
 
I...</description>
			<content:encoded><![CDATA[<div>I want to go Masters program of microelectronics. Which university to choose? Or recomended professor (email etc).<br />
<br />
I from Russia. <br />
<br />
P.S. Not expensive please. Better if have scholarships for foreign students.</div>

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			<category domain="http://www.semiwiki.com/forum/f2/">SemiWiki</category>
			<dc:creator>vadim</dc:creator>
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			<title>NovoBytes MTP Wiki</title>
			<link>http://www.semiwiki.com/forum/showwiki.php?title=Novocell+Semiconductor:NovoBytes+MTP+Wiki&amp;goto=newpost</link>
			<pubDate>Mon, 23 Apr 2012 03:47:07 GMT</pubDate>
			<description>*Hybrid OTP/Multi-time Write: NovoBytes MTP* 
 
Sometimes  your application calls for more than one write. But why...</description>
			<content:encoded><![CDATA[<div><font size="3"><b>Hybrid OTP/Multi-time Write: NovoBytes MTP</b></font><br />
<br />
Sometimes  your application calls for more than one write. But why suffer the  space penalty to cascade your OTP? Why use a 100-1000x write solution if  you only need the ability to rewrite a handful or dozens of times?<br />
<br />
 The answer is Novocell's innovative NovoBytes™ MTP, the most unique  member of Novocell's NovoBlox® NVM IP technology family. Created as a  hybrid between 1000x multi-time programmable and OTP products,   NovoBytes MTP builds on our innovative and uncontested SmartBit™ bit  cell foundation that set the standard for 100% NVM reliability and has  been shown to deliver an unparallelled 30+ years data retention in over  3000 hours of lab testing. NovoBytes MTP is the first multi-time write  antifuse technology to offer off-the-shelf 2, 4, or 8 times write  products and to support almost unlimited writes in custom  configurations. NovoBytes MTP offers an incredible 60% area savings when  compared with multiple cascaded OTP blocks for the same number of  writes.<br />
<br />
<br />
 <img src="http://novocellsemi.com/sites/novocellsemi.com/files/Images/2nTP-BD.jpg" border="0" alt="" /><b><br />
<br />
<br />
<br />
<br />
<br />
<br />
<br />
<br />
<br />
<br />
<br />
<br />
Features</b><br />
<br />
 - Addressable arrays<br />
 - 2, 4, or 8 write cycles<br />
 - 64% Area savings compared with multiple OTP instances<br />
<br />
 <b>Densities: 8 bits to 32K bits</b><br />
<br />
 <b><a href="http://novocellsemi.com/2ntp-faqs" target="_blank">NovoBytes MTP FAQs<br />
</a></b><br />
 <a href="http://novocellsemi.com/sites/novocellsemi.com/files/NovoBytesMTP-Brief.pdf" target="_blank"><b>Download the NovoBytes MTP Product Brief</b></a><br />
<br />
 <b><a href="http://novocellsemi.com/sites/novocellsemi.com/files/2nTP%20Whitepaper_Apr2010.pdf" target="_blank">Read a whitepaper about hybrid OTP/MTP<br />
</a></b><br />
 <b><a href="http://novocellsemi.com/contact" target="_blank">Contact us for more information.</a><br />
</b><br />
<b><a href="http://novocellsemi.com/novocell-otp%20memory%20ip" target="_blank">Back to Products</a></b></div>

]]></content:encoded>
			<category domain="http://www.semiwiki.com/forum/f230/">Novocell Semiconductor Wiki</category>
			<dc:creator>rcnenni</dc:creator>
			<guid isPermaLink="true">http://www.semiwiki.com/forum/showwiki.php?title=Novocell+Semiconductor:NovoBytes+MTP+Wiki</guid>
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		<item>
			<title>NovoHD Wiki</title>
			<link>http://www.semiwiki.com/forum/showwiki.php?title=Novocell+Semiconductor:NovoHD+Wiki&amp;goto=newpost</link>
			<pubDate>Mon, 23 Apr 2012 03:46:43 GMT</pubDate>
			<description><![CDATA[*Ultra-High Density ROM-Style OTP NVM* 
 
 NovoHD is the most recent addition to Novocell's OTP NVM IP  technology...]]></description>
			<content:encoded><![CDATA[<div><b>Ultra-High Density ROM-Style OTP NVM</b><br />
<br />
 NovoHD is the most recent addition to Novocell's OTP NVM IP  technology family, continuing to build on our innovative SmartBit™  bitcell foundation offering six sigma reliability and that has been  tested to deliver an unparallelled 30+ years data retention based on  3000 hours of accelerated life testing.<br />
<br />
 NovoHD blocks can be configured with block densities from 32K to  4Mbits, with 8, 16, or 32 bit bus widths using an area efficient design  with 5-10X faster access times (under 12 nsec), low power sleep mode,  and low programming current needs. And, like all Smartbit-based OTP,  NovoHD programs dynamically until all bits are programmed, eliminating  process related Gaussian tail bit failures, and avoiding the need for  building  redundancy into your designs.<br />
<br />
<br />
 <b><img src="http://novocellsemi.com/sites/novocellsemi.com/files/Images/ROM-BD.jpg" border="0" alt="" /></b><b><br />
<br />
Features</b> <br />
<br />
<ul><li style="">High Density Addressable Arrays</li><li style="">Array scales with LV Transistors</li><li style="">Access times  <12nsec</li><li style="">DONE Programming Signal</li><li style="">Low Power Sleep Mode</li><li style="">Low Programming Current <15mA</li><li style="">No Tail Bit Failures</li><li style="">30+ year Data Retention </li></ul><br />
    <br />
 <b><b>Densities:</b> 32K - 4Mbits  </b><br />
<br />
   <b><a href="http://novocellsemi.com/sites/novocellsemi.com/files/NovoHD-Brief.pdf" target="_blank">Download the ZipMem Product Brief</a></b><br />
 <b><a href="http://novocellsemi.com/contact" target="_blank"><br />
Contact us for more information.</a></b><br />
  <br />
 <b><a href="http://novocellsemi.com/novocell-otp%20memory%20ip" target="_blank">Back to Products</a></b></div>

]]></content:encoded>
			<category domain="http://www.semiwiki.com/forum/f230/">Novocell Semiconductor Wiki</category>
			<dc:creator>rcnenni</dc:creator>
			<guid isPermaLink="true">http://www.semiwiki.com/forum/showwiki.php?title=Novocell+Semiconductor:NovoHD+Wiki</guid>
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			<title>NovoBytes Wiki</title>
			<link>http://www.semiwiki.com/forum/showwiki.php?title=Novocell+Semiconductor:NovoBytes+Wiki&amp;goto=newpost</link>
			<pubDate>Mon, 23 Apr 2012 03:46:21 GMT</pubDate>
			<description>*NovoBytes™ – For All the Write Reasons* 
 
Novocell’s  NovoBytes one-time programmable (OTP) nonvolatile memory IP is...</description>
			<content:encoded><![CDATA[<div><div style="text-align: left;"><b>NovoBytes™ – For All the Write Reasons</b><br />
<br />
Novocell’s  NovoBytes one-time programmable (OTP) nonvolatile memory IP is a NVM  block which can be embedded in standard Logic CMOS without any  additional process steps or post processing, and has the ability to be  programmed at wafer level, in package, or in the field.<br />
</div> <div style="text-align: left;"><br />
NovoBytes, previously known as NovoBlox  Nano, is a new area efficient version of our reliability leading  NovoBlox OTP from 2002. The new NovoBytes product line features space  efficient addressable arrays from 64bit to 32Kbits with a 70% smaller  footprint. Custom aspect ratios are always available, and, like our  pioneering NovoBlox OTP, NovoBytes programs dynamically until all bits  are programmed, eliminating the tail bit failures observed in other OTP  solutions.<br />
<br />
</div> <div style="text-align: left;"><i><a href="http://novocellsemi.com/Novocell%20multi-time%20write%20MTP%20OTP%20innovation%202nTP" target="_blank"><b>NovoBytes MTP</b></a>  is a special version of NovoBytes, providing off-the-shelf 2x, 4x, and  8x multi-time write capabilities, or up to 1000x write in custom  configurations. <a href="http://www.novocellsemi.com/contact" target="_blank">Contact Novocell</a> for details on storage and write options.<br />
<br />
</i><br />
</div> <img src="http://novocellsemi.com/sites/novocellsemi.com/files/Images/ROM-BD.jpg" border="0" alt="" /><b>Features</b><br />
 - Addressable Arrays<br />
- Access Times <8ns<br />
- DONE Programming Signal<br />
- Low Power Sleep Mode<br />
- Low Programming Current <15mA<br />
- No Tail Bit Failures<br />
- 30+ yr Data Retention<br />
  <a href="http://novocellsemi.com/sites/novocellsemi.com/files/NovoBytes-Brief.pdf" target="_blank"><b><br />
<br />
Download the NovoBytes Product Brief</b></a><br />
<a href="http://novocellsemi.com/contact" target="_blank"><b><br />
Contact us for more information.</b><br />
</a><b><br />
 <a href="http://novocellsemi.com/novocell-otp%20memory%20ip" target="_blank">Back to Products</a></b></div>

]]></content:encoded>
			<category domain="http://www.semiwiki.com/forum/f230/">Novocell Semiconductor Wiki</category>
			<dc:creator>rcnenni</dc:creator>
			<guid isPermaLink="true">http://www.semiwiki.com/forum/showwiki.php?title=Novocell+Semiconductor:NovoBytes+Wiki</guid>
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			<title>Novobits SPX Wiki</title>
			<link>http://www.semiwiki.com/forum/showwiki.php?title=Novocell+Semiconductor:Novobits+SPX+Wiki&amp;goto=newpost</link>
			<pubDate>Mon, 23 Apr 2012 03:45:56 GMT</pubDate>
			<description><![CDATA[*The Ideal Trimming and Calibration OTP NVM Choice* 
  
NovoBits is a trimming, &amp; calibration product built on our...]]></description>
			<content:encoded><![CDATA[<div><div style="text-align: left;"><b>The Ideal Trimming and Calibration OTP NVM Choice</b></div> <div style="text-align: left;"><br />
NovoBits is a trimming, &amp; calibration product built on our patented and uncontested Novocell SmartBit™ technology, offering unmatched 100% reliability and is Novocell’s feature rich alternative to efuse OTP NVM.<br />
</div> <br />
NovoBits blocks are an area-efficient solution made up of dense 8 bit modular blocks that can meet the smallest of OTP needs with convenience features Preview mode, low power sleep mode, low programming current needs, and unequalled 30+ years of data retention. And, since it is based on our foundational SmartBit technology, NovoBits programs dynamically until all bits are programmed, absolutely ensuring no troublesome tail bit failures, and eliminating the need for building memory redundancy into your  designs.<br />
  <br />
 <img src="http://novocellsemi.com/sites/novocellsemi.com/files/Images/Serial-BD.jpg" border="0" alt="" /><b><br />
<br />
<br />
Features</b><br />
 - Serial interface IN/OUT<br />
 - Maintained Parallel Outputs<br />
 - Preview Mode<br />
 - Cascadable<br />
  <br />
 <b>Densities: 32-256 bits</b><br />
  <br />
 <a href="http://novocellsemi.com/sites/novocellsemi.com/files/NovobitsSPX-Brief.pdf" target="_blank"><b><br />
<br />
<br />
<br />
Download the NovoBlox Serial Product Brief</b></a><br />
<br />
 <b><a href="http://novocellsemi.com/novobits-vs-serial" target="_blank"><br />
Compare to NovoBits</a></b><br />
<br />
 <b><a href="http://novocellsemi.com/contact" target="_blank"><br />
Contact us for more information.</a></b><br />
<br />
 <b><a href="http://novocellsemi.com/novocell-otp%20memory%20ip" target="_blank"><br />
Back to Products</a></b></div>

]]></content:encoded>
			<category domain="http://www.semiwiki.com/forum/f230/">Novocell Semiconductor Wiki</category>
			<dc:creator>rcnenni</dc:creator>
			<guid isPermaLink="true">http://www.semiwiki.com/forum/showwiki.php?title=Novocell+Semiconductor:Novobits+SPX+Wiki</guid>
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			<title>NovoBits Wiki</title>
			<link>http://www.semiwiki.com/forum/showwiki.php?title=Novocell+Semiconductor:NovoBits+Wiki&amp;goto=newpost</link>
			<pubDate>Mon, 23 Apr 2012 03:45:29 GMT</pubDate>
			<description>*Reliability. Yield. Size. Advantage: NovoBits.* 
 
NovoBits  is a customizable register product built on our patented...</description>
			<content:encoded><![CDATA[<div><font color="#000000"><b>Reliability. Yield. Size. Advantage: NovoBits.</b></font><br />
<br />
NovoBits  is a customizable register product built on our patented and  unchallenged Novocell SmartBit™ technology and is Novocell’s alternative  to foundry-specific e-fuse.<br />
NovoBits blocks are an area-efficient  solution made up of dense 8 bit modular blocks that can meet the  smallest of OTP needs with convenience features like 5-10X faster access  times, low power sleep mode, low programming current needs, and  unequalled 30+ years of data retention. And, just like our original OTP  NVM, NovoBits programs dynamically until all bits are programmed,  absolutely ensuring no troublesome tail bit failures, and eliminating  the need for building redundancy into your designs.<br />
<br />
 <img src="http://novocellsemi.com/sites/novocellsemi.com/files/Images/NovoBits-BD.jpg" border="0" alt="" /><b>Features</b><br />
 - Register architecture<br />
 - Parallel IN / Parallel OUT<br />
 - Alternative to foundry e-fuse<br />
  <br />
  <br />
 <b>Densities: Novobits is available in 8 bit increments from 8-256 bits; <br />
other  Novobits variations are available to 512bits with optional Serial  Interface or Preview Mode wrappers--contact your Swift2Chip account  engineer for details.</b><br />
 <i>Also see our Novobits SPX product for Trimming and Calibration applications, with Serial and Preview Mode already included.</i><br />
 <a href="http://novocellsemi.com/sites/novocellsemi.com/files/NovoBits-Brief_0.pdf" target="_blank"><b><br />
Download the NovoBits Product Brief</b></a><br />
<br />
 <b><a href="http://novocellsemi.com/novobits-vs-serial" target="_blank"><br />
Compare to NovoBlox Serial</a></b><br />
<br />
  <b><a href="http://novocellsemi.com/novocell-otp%20memory%20ip" target="_blank">Back to Products</a></b><br />
  <br />
 <b><a href="http://novocellsemi.com/contact" target="_blank">Contact us for more information.</a></b></div>

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			<category domain="http://www.semiwiki.com/forum/f230/">Novocell Semiconductor Wiki</category>
			<dc:creator>rcnenni</dc:creator>
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			<title>SWIFT2Chip Wiki</title>
			<link>http://www.semiwiki.com/forum/showwiki.php?title=Novocell+Semiconductor:SWIFT2Chip+Wiki&amp;goto=newpost</link>
			<pubDate>Mon, 23 Apr 2012 03:44:58 GMT</pubDate>
			<description>*Innovation in Bringing NVM to Market--Hassle Free* 
 
Novocell’s  new SWIFT2Chip program delivers any of our...</description>
			<content:encoded><![CDATA[<div><b><i>Innovation in Bringing NVM to Market--Hassle Free</i></b><br />
<br />
Novocell’s  new SWIFT2Chip program delivers any of our non-volatile memory  intellectual property (IP) block products to clients as a complete  turn-key solution that includes all the necessary read, write, and  programming circuitry.  Unlike competitive OTP NVM solutions, no  external charge pump or additional voltage is required.  The IP also  features a logic “DONE” signal for programming verification, to ensure  completion of the firm’s guaranteed-reliable programming cycle.   However, SWIFT2Chip means not just technology, but complete,  comprehensive end-to-end support, delivered through immediate access to  complete, accurate and timely documentation, flexible business model  negotiations, an assigned and dedicated account engineer, and even  on-demand design reviews at client request.<br />
<br />
SWIFT2Chip  has been designed to provide this full-service program to provide loyal  Novocell NVM IP customers with unmatched support and flexibility. By  providing the distinctive NovoBlox™ NVM to customers within an  end-to-end support structure that provides for integrated assistance  with special customer needs, on-call detailed information, design  reviews and library files, Novocell is again setting a new standard for  service in the same way the NovoBlox SmartBit NVM technology set the  standard for 100% nonvolatile memory reliability when it was introduced  nearly ten years ago.<br />
<br />
<br />
<a href="http://novocellsemi.com/sites/novocellsemi.com/files/SWIFT2Chip-Brief_1.pdf" target="_blank"><b><br />
SWIFT2Chip Product Brief</b></a></div>

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			<category domain="http://www.semiwiki.com/forum/f230/">Novocell Semiconductor Wiki</category>
			<dc:creator>rcnenni</dc:creator>
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			<title>NVM White Papers Wiki</title>
			<link>http://www.semiwiki.com/forum/showwiki.php?title=Novocell+Semiconductor:NVM+White+Papers+Wiki&amp;goto=newpost</link>
			<pubDate>Mon, 23 Apr 2012 03:43:37 GMT</pubDate>
			<description>Put the Most Reliable NVM on Your Silicon! 
 
Novocell Semiconductor developed our SmartBits™ NVM technology over ten...</description>
			<content:encoded><![CDATA[<div>Put the Most Reliable NVM on Your Silicon!<br />
<br />
Novocell Semiconductor developed our SmartBits™ NVM technology over ten years ago, and secured the patent to the innovative and unique design and process in 2004. The IP is available at all major foundries, and has been qualified from .35&#956;m to 45nm. Plus, the technology is fully scalable down to 28nm and beyond. Our OTP and new Multi-Time Programmable (2nTP™) IP provides non-volatile memory blocks that can be embedded in standard Logic CMOS without any additional process or post-process steps, and can be programmed at the wafer level, in package, or in the field, as end use requires. When You Choose Novocell, You Choose the Leader. Novocell is the innovator in antifuse one-time programmable memory–since 2001. Our long term patents have never been challenged, and our exclusive tech nology’s 100% reliablity remains unequaled.<br />
<br />
Download a White Paper to learn more about Novocell's leadership in Non-Volatile Memory IP:<br />
<i>(Each PDF requires Adobe Acrobat)<br />
</i><br />
<br />
 <a href="http://novocellsemi.com/sites/novocellsemi.com/files/Importance%20of%20Dynamic%20Programming%20in%20AntiFuse%20Technology.pdf" target="_blank">Importance of Dynamic Programming in Detecting Hard Breakdown in Anti-fuse Technology</a><br />
  <br />
 <a href="http://novocellsemi.com/sites/novocellsemi.com/files/2nTP%20Whitepaper_Apr2010.pdf" target="_blank">The Industry's First Hybrid MTP/OTP Solution: Novocell's 2nTP NVM Solution</a></div>

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			<dc:creator>rcnenni</dc:creator>
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			<title>Novocell Semiconductor</title>
			<link>http://www.semiwiki.com/forum/showwiki.php?title=Novocell+Semiconductor:Novocell+Semiconductor&amp;goto=newpost</link>
			<pubDate>Mon, 23 Apr 2012 03:41:27 GMT</pubDate>
			<description>NOVOCELL, formerly Intelligent Micro Design,  founded in 2001, has become the foundation of a growing semiconductor ...</description>
			<content:encoded><![CDATA[<div><font size="2"><span style="font-family: tahoma">NOVOCELL, formerly Intelligent Micro Design,  founded in 2001, has become the foundation of a growing semiconductor  industry in the Pittsburgh region. In 2005, Novocell moved its  headquarters to the recently constructed LindenPointe Innovative  Business Campus, a 115-acre planned technical park. <br />
<br />
As a member of The  Pittsburgh Technology Collaborative (TTC), Novocell maintains a strong  network of technical experts throughout the world which it leverages to  drive innovation in its solutions. Included in this network are  researchers and developers from Carnegie Mellon University, Penn State  University, The University of Pittsburgh and other TTC member companies.<br />
 <a href="http://novocellsemi.com/driving-directions" target="_blank"><br />
Map and Driving Directions</a><br />
<br />
<br />
<font color="#009933"><b>Novocell's Design Philosophy</b></font><br />
<br />
 NovoBlox was designed with  the goal of creating one of the most highly reliable memory IPs on the  market.When developing NovoBlox, Novocell's design team ensured that  reliability was never compromised.<br />
<br />
 Conscious tradeoffs were  made in the design of NovoBlox specifically size for reliability.  Novocell is not interested in having the smallest memory IP on the  market, but we do want to ensure that we have the most reliable. While  similar memory products may take up less space on an IC, there is no  guarantee that the memories will superiorly perform 100% of the time.<br />
<br />
 To maximize reliability,  the breakdown voltage in NovoBlox is contained entirely within the  memory core guaranteeing that only the programmed cells see high  voltage. The reliability of unprogrammed cells or other devices on the  IC are not negatively impacted with Novocell's design methodology.  NovoBlox also features a dynamic (not statically-timed) write protocol  with active sensing which ensures hard breakdown of the gate oxide and  the creation of a permanent short between the gate polysilicon and the  channel of a programmed device.</span></font></div>

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